MC68HC08AZ32A Datasheet, PDF (176/456 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Low Voltage Inhibit (LVI)
LVIRST bits must be at ‘1’ to enable the LVI module and to enable LVI
resets.
13.4.3 False Reset Protection
The V_DD pin level is digitally filtered to reduce false resets due to power
supply noise. In order for the LVI module to reset the MCU,V_DD must
remain at or below the LVI_TRIPF level for 9 or more consecutive CPU
cycles. V_DD must be above LVI_TRIPR for only one CPU cycle to bring the
MCU out of reset.
13.5 LVI Status Register (LVISR)
The LVI status register flags V_DD voltages below the LVI_TRIPF level.
Bit 7
6
5
4
3
2
1
Bit 0
LVISR ^{Read: LVIOUT}
0
0
0
0
0
0
0
$FE0F _Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 13-2. LVI Status Register (LVISR)
LVIOUT — LVI Output Bit
This read-only flag becomes set when V_DD falls below the LVI_TRIPF
voltage for 32-40 CGMXCLK cycles. (See Table 13-2). Reset clears
the LVIOUT bit.
Technical Data
176
MC68HC08AZ32A — Rev 1.0
Low Voltage Inhibit (LVI)
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