MC68HC08AZ32A Datasheet, PDF (243/456 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Serial Peripheral Interface (SPI)
Interrupts
bit does not clear the SPE bit or reset the SPI in any way. Software can
abort the SPI transmission by toggling the SPE bit of the slave.
NOTE:
A logic ‘1’ on the SS pin of a slave SPI puts the MISO pin in a high
impedance state. Also, the slave SPI ignores all incoming SPSCK
clocks, even if a transmission has begun.
To clear the MODF flag, read the SPSCR and then write to the SPCR
register. This entire clearing procedure must occur with no MODF
condition existing or else the flag will not be cleared.
16.7 Interrupts
Four SPI status flags can be enabled to generate CPU interrupt
requests:
Table 16-3. SPI Interrupts
Flag
Request
SPTE (Transmitter Empty) SPI Transmitter CPU Interrupt Request (SPTIE = 1)
SPRF (Receiver Full)
SPI Receiver CPU Interrupt Request (SPRIE = 1)
OVRF (Overflow)
SPI Receiver/Error Interrupt Request (SPRIE = 1, ERRIE = 1)
MODF (Mode Fault)
SPI Receiver/Error Interrupt Request (SPRIE = 1, ERRIE = 1, MODFEN = ‘1’)
The SPI transmitter interrupt enable bit (SPTIE) enables the SPTE flag
to generate transmitter CPU interrupt requests.
The SPI receiver interrupt enable bit (SPRIE) enables the SPRF bit to
generate receiver CPU interrupt requests, provided that the SPI is
enabled (SPE = 1).
The error interrupt enable bit (ERRIE) enables both the MODF and
OVRF flags to generate a receiver/error CPU interrupt request.
The mode fault enable bit (MODFEN) can prevent the MODF flag from
being set so that only the OVRF flag is enabled to generate
receiver/error CPU interrupt requests.
MC68HC08AZ32A — Rev 1.0
MOTOROLA
Serial Peripheral Interface (SPI)
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Technical Data
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