MC68HC908KX8 Datasheet, PDF (86/310 Pages) Motorola, Inc – Microcontrollers

System Integration Module (SIM)
6.4.1.5 Forced Monitor Mode Entry Reset (MENRST)
The MENRST module is monitoring the reset vector fetches and will
assert an internal reset if it detects that the reset vectors are erased
($FF). When the MCU comes out of reset, it is forced into monitor mode.
See Section 18. Monitor ROM (MON).
6.4.1.6 Low-Voltage Inhibit (LVI) Reset
The low-voltage inhibit module (LVI) asserts its output to the SIM when
the V_DD voltage falls to the V_TRIPF voltage. The LVI bit in the SIM reset
status register (SRSR) is set and a chip reset is asserted if the LVIPWRD
and LVIRSTD bits in the CONFIG register are at logic 0. The MCU is
held in reset until V_DD rises above V_TRIPR. The MCU remains in reset
until the SIM counts 4096 CGMXCLK to begin a reset recovery. Another
64 CGMXCLK cycles later, the CPU is released from reset to allow the
reset vector sequence to occur. See Section 8. Low-Voltage Inhibit
(LVI).
6.5 SIM Counter
The SIM counter is used by the power-on reset module (POR) and in
stop mode recovery to allow the oscillator time to stabilize before
enabling the internal bus (IBUS) clocks. The SIM counter also serves as
a prescaler for the computer operating properly module (COP). The SIM
counter overflow supplies the clock for the COP module. The SIM
counter is 12 bits long and is clocked by the falling edge of CGMXCLK.
6.5.1 SIM Counter During Power-On Reset
The power-on reset module (POR) detects power applied to the MCU.
At power-on, the POR circuit asserts the signal PORRST. Once the SIM
is initialized, it enables the internal clock generator to drive the bus clock
state machine.
Technical Data
86
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 — Rev. 1.0
System Integration Module (SIM)
MOTOROLA