MC68HC908KX8 Datasheet, PDF (118/310 Pages) Motorola, Inc – Microcontrollers

Internal Clock Generator Module (ICG)
7.5.3 Using Clock Monitor Interrupts
The clock monitor circuit can be used to recover from perilous situations
such as crystal loss. To use the clock monitor effectively, these points
should be observed:
• Enable the clock monitor and clock monitor interrupts.
• The first statement in the clock monitor interrupt service routine
(CMISR) should be a read to the ICG control register (ICGCR) to
verify that the clock monitor flag (CMF) is set. This is also the first
step in clearing the CMF bit.
• The second statement in the CMISR should be a write to the
ICGCR to clear the CMF bit (write the bit low). Writing the bit high
will not affect it. This statement does not need to immediately
follow the first, but must be contained in the CMISR.
• The third statement in the CMISR should be to clear the CMON bit.
This is required to ensure proper reconfiguration of the reference
dividers. This statement also must be contained in the CMISR.
• Although the clock monitor can be enabled only when both clocks
are stable (ICGS is set or ECGS is set), it will remain set if one of
the clocks goes unstable.
• The clock monitor only works if the external slow (EXTSLOW) bit
in the CONFIG or MOR is set to the correct value.
• The internal and external clocks must both be enabled and
running to use the clock monitor.
• When the clock monitor detects inactivity, the inactive clock is
automatically deselected and the active clock selected as the
source for CGMXCLK and TBMCLK. The CMISR can use the
state of the CS bit to check which clock is inactive.
• When the clock monitor detects inactivity, the application may
have been subjected to extreme conditions which may have
affected other circuits. The CMISR should take any appropriate
precautions.
Technical Data
118
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 — Rev. 1.0
Internal Clock Generator Module (ICG)
MOTOROLA