MC68HC908KX8 Datasheet, PDF (233/310 Pages) Motorola, Inc – Microcontrollers

Timer Interface Module (TIM)
Interrupts
Setting MS0B links channels 0 and 1 and configures them for buffered
PWM operation. The TIM channel 0 registers (TCH0H and TCH0L)
initially control the buffered PWM output. TIM status control register 0
(TSCR0) controls and monitors the PWM signal from the linked
channels.
Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIM
overflows. Subsequent output compares try to force the output to a state
it is already in and have no effect. The result is a 0 percent duty cycle
output.
Setting the channel x maximum duty cycle bit (CHxMAX) and setting the
TOVx bit generates a 100 percent duty cycle output. See 16.8.4 TIM
Channel Status and Control Registers.
16.5 Interrupts
These TIM sources can generate interrupt requests:
• TIM overflow flag (TOF) — The timer overflow flag (TOF) bit is set
when the TIM counter reaches the modulo value programmed in
the TIM counter modulo registers. The TIM overflow interrupt
enable bit, TOIE, enables TIM overflow interrupt requests. TOF
and TOIE are in the TIM status and control registers.
• TIM channel flags (CH1F and CH0F) — The CHxF bit is set
when an input capture or output compare occurs on channel x.
Channel x TIM CPU interrupt requests are controlled by the
channel x interrupt enable bit, CHxIE. Channel x TIM CPU
interrupt requests are enabled when CHxIE = 1. CHxF and CHxIE
are in the TIM channel x status and control register.
16.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-
consumption standby modes.
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 — Rev. 1.0
MOTOROLA
Timer Interface Module (TIM)
Technical Data
233