MC68HC908KX8 Datasheet, PDF (241/310 Pages) Motorola, Inc – Microcontrollers

Timer Interface Module (TIM)
I/O Registers
NOTE:
Before changing a channel function by writing to the MS0B or MSxA bit,
set the TSTOP and TRST bits in the TIM status and control register
(TSC).
ELSxB and ELSxA — Edge/Level Select Bits
When channel x is an input capture channel, these read/write bits
control the active edge-sensing logic on channel x.
When channel x is an output compare channel, ELSxB and ELSxA
control the channel x output behavior when an output compare
occurs.
When ELSxB and ELSxA are both clear, channel x is not connected
to port A, and pin PTAx/TCHx is available as a general-purpose I/O
pin. Table 16-2 shows how ELSxB and ELSxA work. Reset clears the
ELSxB and ELSxA bits.
Table 16-2. Mode, Edge, and Level Selection
MSxB:MSxA ELSxB:ELSxA
Mode
Configuration
X0
00
Pin under port control;
initial output level high
Output preset
X1
00
Pin under port control;
initial output level low
00
01
Capture on rising edge only
00
10
Input capture ^{Capture on falling edge only}
00
11
Capture on rising or
falling edge
01
01
Toggle output on compare
Output
01
10
compare or Clear output on compare
PWM
01
11
Set output on compare
1X
01
Toggle output on compare
Buffered output
1X
10
compare or Clear output on compare
buffered PWM
1X
11
Set output on compare
NOTE: Before enabling a TIM channel register for input capture operation, make
sure that the PTAx/TCHx pin is stable for at least two bus clocks.
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 — Rev. 1.0
MOTOROLA
Timer Interface Module (TIM)
Technical Data
241