MC68HC908KX8 Datasheet, PDF (243/310 Pages) Motorola, Inc – Microcontrollers

Timer Interface Module (TIM)
I/O Registers
16.8.5 TIM Channel Registers
These read/write registers (TCH0H/L and TCH1H/L) contain the
captured TIM counter value of the input capture function or the output
compare value of the output compare function. The state of the TIM
channel registers after reset is unknown.
In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the
TIM channel x registers (TCHxH) inhibits input captures until the low
byte (TCHxL) is read.
In output compare mode (MSxB:MSxA ≠ 0:0), writing to the high byte of
the TIM channel x registers (TCHxH) inhibits output compares until the
low byte (TCHxL) is written.
Register name and address: TCH0H — $0026
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 15
14
13
12
11
10
Write:
9
Bit 8
Reset:
Indeterminate after reset
Register name and address: TCH0L — $0027
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 7
6
5
4
3
2
1
Bit 0
Write:
Reset:
Indeterminate after reset
Register name and address: TCH1H — $0029
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 15
14
13
12
11
10
Write:
9
Bit 8
Reset:
Indeterminate after reset
Register name and address: TCH1L — $002A
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 7
6
5
4
3
2
1
Bit 0
Write:
Reset:
Indeterminate after reset
Figure 16-9. TIM Channel Registers (TCH0H/L and TCH1H/L)
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 — Rev. 1.0
MOTOROLA
Timer Interface Module (TIM)
Technical Data
243