MC68HC908KX8 Datasheet, PDF (169/310 Pages) Motorola, Inc – Microcontrollers

External Interrupt (IRQ)
IRQ Status and Control Register
Address: $001D
Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
0
0
0
IRQF1
0
IMASK1 MODE1
Write: R
R
R
R
R
ACK1
Reset: 0
0
0
0
U
0
0
0
R = Reserved
U = Unaffected
Figure 12-2. IRQ Status and Control Register (ISCR)
IRQF1 — IRQ1 Flag Bit
This read-only status bit is high when the IRQ1 interrupt is pending.
1 = IRQ1 interrupt pending
0 = IRQ1 interrupt not pending
ACK1 — IRQ1 Interrupt Request Acknowledge Bit
Writing a logic 1 to this write-only bit clears the IRQ1 latch. ACK1
always reads as logic 0. Reset clears ACK1.
IMASK1 — IRQ1 Interrupt Mask Bit
Writing a logic 1 to this read/write bit disables IRQ1 interrupt requests.
Reset clears IMASK1.
1 = IRQ1 interrupt requests disabled
0 = IRQ1 interrupt requests enabled
MODE1 — IRQ1 Edge/Level Select Bit
This read/write bit controls the triggering sensitivity of the IRQ1 pin.
Reset clears MODE1.
1 = IRQ1 interrupt requests on falling edges and low levels
0 = IRQ1 interrupt requests on falling edges only
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 — Rev. 1.0
MOTOROLA
External Interrupt (IRQ)
Technical Data
169