MC68HC908KX8 Datasheet, PDF (239/310 Pages) Motorola, Inc – Microcontrollers

Timer Interface Module (TIM)
I/O Registers
16.8.4 TIM Channel Status and Control Registers
Each of the TIM channel status and control registers (TSC0 and TSC1):
• Flags input captures and output compares
• Enables input capture and output compare interrupts
• Selects input capture, output compare, or PWM operation
• Selects high, low, or toggling output on output compare
• Selects rising edge, falling edge, or any edge as the active input
capture trigger
• Selects output toggling on TIM overflow
• Selects 0 percent and100 percent PWM duty cycle
• Selects buffered or unbuffered output compare/PWM operation
Register name and address: TSC0 — $0025
Bit 7
6
5
4
Read: CH0F
Write: 0
CH0IE
MS0B
MS0A
Reset: 0
0
0
0
3
2
ELS0B ELS0A
0
0
1
Bit 0
TOV0 CH0MAX
0
0
Register name and address: TSC1 — $0028
Bit 7
6
5
4
3
2
1
Read: CH1F
0
CH1IE
MS1A ELS1B ELS1A TOV1
Write: 0
Reset: 0
0
0
0
0
0
0
= Unimplemented
Figure 16-7. TIM Channel Status and Control
Registers (TSC0 and TSC1)
Bit 0
CH1MAX
0
CHxF — Channel x Flag Bit
When channel x is an input capture channel, this read/write bit is set
when an active edge occurs on the channel x pin. When channel x is
an output compare channel, CHxF is set when the value in the TIM
counter registers matches the value in the TIM channel x registers.
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 — Rev. 1.0
MOTOROLA
Timer Interface Module (TIM)
Technical Data
239