MC68HC908KX8 Datasheet, PDF (120/310 Pages) Motorola, Inc – Microcontrollers

Internal Clock Generator Module (ICG)
Table 7-2. Quantization Error in ICLK (Continued)
DDIV[3:0]
%0010
%0010
%0010
%0011
%0011
%0100
%0100
%0101–%1001 (max)
ICLK Cycles
1
4
≥8
1
≥4
1
≥2
≥1
Bus Cycles
NA
1
≥2
NA
≥1
NA
≥1
≥1
τ_ICLK Q-ERR
1.61%–2.94%
0.403%–0.735%
0.202%–0.368%
0.806%–1.47%
0.202%–0.368%
0.403%–0.735%
0.202%–0.368%
0.202%–0.368%
7.5.4.2 Binary Weighted Divider
The binary weighted divider divides the output of the ring oscillator by a
power of two, specified by the DCO divider control bits (DDIV[3:0]). DDIV
maximizes at %1001 (values of %1010 through %1111 are interpreted
as %1001), which corresponds to a divide by 512. When DDIV is %0000,
the ring oscillator’s output is divided by 1. Incrementing DDIV by one will
double the period; decrementing DDIV will halve the period. The DLF
cannot directly increment or decrement DDIV; DDIV is only incremented
or decremented when an addition or subtraction to DSTG carries or
borrows.
7.5.4.3 Variable-Delay Ring Oscillator
The variable-delay ring oscillator’s period is adjustable from 17 to 31
stage delays, in increments of two, based on the upper three DCO stage
control bits (DSTG[7:5]). A DSTG[7:5] of %000 corresponds to 17 stage
delays; DSTG[7:5] of %111 corresponds to 31 stage delays. Adjusting
the DSTG[5] bit has a 6.45 percent to 11.8 percent effect on the output
frequency. This also corresponds to the size correction made when the
frequency error is greater than ±15 percent. The value of the binary
weighted divider does not affect the relative change in output clock
period for a given change in DSTG[7:5].
Technical Data
120
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 — Rev. 1.0
Internal Clock Generator Module (ICG)
MOTOROLA