MC68HC908KX8 Datasheet, PDF (128/310 Pages) Motorola, Inc – Microcontrollers

Internal Clock Generator Module (ICG)
EXTXTALEN, when set, also configures the external clock stabilization
divider in the clock monitor for a 4096 cycle timeout to allow the proper
stabilization time for a crystal. When EXTXTALEN is clear, the
stabilization divider is configured to 16 cycles since an external clock
source does not need a startup time.
The default state for this option is clear.
7.7.3 Slow External Clock (EXTSLOW)
Slow external clock (EXTSLOW), when set, will decrease the drive
strength of the oscillator amplifier, enabling low-frequency crystal
operation (30 kHz–100 kHz) if properly enabled with the external clock
enable (EXTCLKEN) and external crystal enable (EXTXTALEN) bits.
When clear, EXTSLOW enables high-frequency crystal operation
(1 MHz to 8 MHz).
EXTSLOW, when set, also configures the clock monitor to expect an
external clock source that is slower than the low-frequency base clock
(60 Hz to 307.2 kHz). When EXTSLOW is clear, the clock monitor will
expect an external clock faster than the low-frequency base clock
(307.2 kHz to 32 MHz).
The default state for this option is clear.
7.7.4 Oscillator Enable In Stop (OSCENINSTOP)
Oscillator enable in stop (OSCENINSTOP), when set, will enable the
ICG to continue to generate clocks (either CGMXCLK, CGMOUT, or
TBMCLK) in stop mode. This function is used to keep the timebase
running while the rest of the microcontroller stops. When
OSCENINSTOP is clear, all clock generation will cease and CGMXCLK,
CGMOUT, and TBMCLK will be forced low during stop mode.
The default state for this option is clear.
Technical Data
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MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 — Rev. 1.0
Internal Clock Generator Module (ICG)
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