MC68HC908KX8 Datasheet, PDF (163/310 Pages) Motorola, Inc – Microcontrollers

Computer Operating Properly Module (COP)
COP Control Register
11.6 COP Control Register
The COP control register (COPCTL) is located at address $FFFF and
overlaps the reset vector. Writing any value to $FFFF clears the COP
counter and stages 12–5 of the COP prescaler and starts a new timeout
period. Reading location $FFFF returns the low byte of the reset
vector.
Address: $FFFF
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Low byte of reset vector
Write:
Clear COP counter
Reset:
Unaffected by reset
Figure 11-2. COP Control Register (COPCTL)
11.7 Interrupts
The COP does not generate CPU interrupt requests.
11.8 Monitor Mode
The COP is disabled in monitor mode when V_TST is present on the IRQ1
pin.
11.9 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-
consumption standby modes.
11.9.1 Wait Mode
The COP remains active in wait mode. To prevent a COP reset during
wait mode, periodically clear the COP counter in a CPU interrupt routine.
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 — Rev. 1.0
MOTOROLA
Computer Operating Properly Module (COP)
Technical Data
163