MC68HC908KX8 Datasheet, PDF (251/310 Pages) Motorola, Inc – Microcontrollers

Analog-to-Digital Converter (ADC)
I/O Registers
17.8.1 ADC Status and Control Register
The following paragraphs describe the function of the ADC status and
control register (ADSCR).
Address: $003C
Bit 7
6
5
4
3
2
1
Bit 0
Read: COCO
AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0
Write: R
Reset: 0
0
0
1
1
1
1
1
R = Reserved
Figure 17-2. ADC Status and Control Register (ADSCR)
COCO — Conversions Complete Bit
When the AIEN bit is a logic 0, the COCO is a read-only bit which is
set each time a conversion is completed. This bit is cleared whenever
the ADC status and control register is written or whenever the ADC
data register is read.
When the AIEN bit is a logic 1, the ADC module is capable of
generating a CPU interrupt after each ADC conversion. A CPU
interrupt is generated if the COCO bit (ADC status control register,
$003C) is at logic 0. If the COCO bit is at logic 1, a DMA interrupt is
generated. Reset clears this bit.
1 = Conversion completed (AIEN = 0)
0 = Conversion not completed (AIEN = 0)
or CPU interrupts enabled (AIEN = 1)
NOTE: Because the MC68HC908KX8 does not have a DMA module, the COCO
bit should not be set while interrupts are enabled (AIEN = 1).
AIEN — ADC Interrupt Enable Bit
When this bit is set, an interrupt is generated at the end of an ADC
conversion. The interrupt signal is cleared when the ADR register is
read or the ADSCR register is written. Reset clears the AIEN bit.
1 = ADC interrupt enabled
0 = ADC interrupt disabled
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 — Rev. 1.0
MOTOROLA
Analog-to-Digital Converter (ADC)
Technical Data
251