MC68HC908KX8 Datasheet, PDF (253/310 Pages) Motorola, Inc – Microcontrollers

Analog-to-Digital Converter (ADC)
I/O Registers
17.8.2 ADC Data Register
One 8-bit result register is provided. This register is updated each time
an ADC conversion completes.
Address: $003D
Bit 7
6
5
4
3
2
1
Bit 0
Read: AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
Write: R
R
R
R
R
R
R
R
Reset:
Indeterminate after reset
R = Reserved
Figure 17-3. ADC Data Register (ADR)
17.8.3 ADC Input Clock Register
This register selects the clock frequency for the ADC.
Address: $003E
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
ADIV2 ADIV1 ADIV0 ADICLK
R
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
R = Reserved
Figure 17-4. ADC Input Clock Register (ADICLK)
ADIV2–ADIV0 — ADC Clock Prescaler Bits
ADIV2, ADIV1, and ADIV0 form a 3-bit field which selects the divide
ratio used by the ADC to generate the internal ADC clock.
Table 17-2 shows the available clock configurations. The ADC clock
should be set to approximately 1 MHz.
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 — Rev. 1.0
MOTOROLA
Analog-to-Digital Converter (ADC)
Technical Data
253