MC68HC908KX8 Datasheet, PDF (124/310 Pages) Motorola, Inc – Microcontrollers

Internal Clock Generator Module (ICG)
usable, although the error will be as high as 5 percent. The total time to
this point is:
τ₅ = abs[44N(τ₁ – τ₂)] + 32τ_IBASE
7.5.6.3 Total Settling Time
Once the clock period is within 5 percent of the desired clock period, the
filter starts making minimum adjustments. In this mode, each correction
will adjust the frequency between 0.202 percent and 0.368 percent. A
maximum of 24 corrections will be required to get to the minimum error.
Each correction takes approximately the same period of time, or
4*τ_IBASE. Added to the corrections for 15 percent to 5 percent, this
makes 32 corrections (128*τ_IBASE) to get from 15 percent to the
minimum error. The total time to the minimum error is:
τ_tot = abs[44N(τ₁ – τ₂)] + 128τ_IBASE
The equations for τ₁₅, τ₅, and τ_tot are dependent on the actual initial and
final clock periods τ₁ and τ₂, not the nominal. This means the variability
in the ICLK frequency due to process, temperature, and voltage must be
considered. Additionally, other process factors and noise can affect the
actual tolerances of the points at which the filter changes modes. This
means a worst case adjustment of up to 35 percent (ICLK clock period
tolerance plus 10 percent) must be added. This adjustment can be
reduced with trimming. Table 7-3 shows some typical values for settling
time.
Table 7-3. Typical Settling Time Examples
τ₁
1/ (6.45 MHz)
1/ (25.8 MHz)
1/ (25.8 MHz)
1/ (307.2 kHz)
τ₂
1/ (25.8 MHz)
1/ (6.45 MHz)
1/ (307.2 kHz)
1/ (25.8 MHz)
N
τ₁₅
84 430 µs
21 107 µs
1
141 µs
84 11.9 ms
τ₅
535 µs
212 µs
246 µs
12.0 ms
τ_tot
850 µs
525 µs
560 µs
12.3 ms
Technical Data
124
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 — Rev. 1.0
Internal Clock Generator Module (ICG)
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