MC68HC908KX8 Datasheet, PDF (270/310 Pages) Motorola, Inc – Microcontrollers

Break (BRK) Module
19.3 Features
Features of the break module include:
• Accessible input/output (I/O) registers during the break interrupt
• Central processor unit (CPU) generated break interrupts
• Software generated break interrupts
• Computer operating properly (COP) disabling during break
interrupts
19.4 Functional Description
When the internal address bus matches the value written in the break
address registers, the break module issues a breakpoint signal to the
CPU. The CPU then loads the instruction register with a software
interrupt instruction (SWI) after completion of the current CPU
instruction. The program counter vectors to $FFFC and $FFFD ($FEFC
and $FEFD in monitor mode).
These events can cause a break interrupt to occur:
• A CPU-generated address (the address in the program counter)
matches the contents of the break address registers.
• Software writes a logic 1 to the BRKA bit in the break status and
control register.
When a CPU-generated address matches the contents of the break
address registers, the break interrupt begins after the CPU completes its
current instruction. A return-from-interrupt instruction (RTI) in the break
routine ends the break interrupt and returns the MCU to normal
operation. Figure 19-1 shows the structure of the break module.
Technical Data
270
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 — Rev. 1.0
Break (BRK) Module
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