MC68HC908KX8 Datasheet, PDF (257/310 Pages) Motorola, Inc – Microcontrollers

Monitor ROM (MON)
Monitor Mode Entry
mode pins are configured appropriately. A second method, intended for
in-circuit programming applications, will force entry into monitor mode
without requiring high voltage on the IRQ1 pin when the reset vector
locations of the FLASH are erased ($FF).
Both of these methods require that the PTA1 pin be pulled low for the
first 24 CGMXCLK cycles after the part comes out of reset. This check
is used by the monitor code to configure the MCU for serial
communication.
18.5.1 Normal Monitor Mode
Normal monitor mode is useful for MCU evaluation, factory testing, and
development tool programming operation. Figure 18-1 shows an
example circuit used for normal monitor mode. Table 18-1 shows the pin
conditions for entering this mode.
Table 18-1. Monitor Mode Entry
$FFFE/
$FFFF
IRQ1
Pin
PTB1 Pin
(PTXMOD1)
PTB0 Pin PTA1 PTA0
(PTXMOD0) Pin Pin
CGMOUT
Bus
Frequency
(f_OP)
X
V_TST
0
1
0
1
C-----G-----M----2-X----C----L---K--- C-----G----M---2---O----U----T---
$FF
blank
V_DD
X
X
0
1
C-----G-----M----2-X----C----L---K--- C-----G----M---2---O----U----T---
NOTE:
PTA1 = 0 and PTA0 = 1 allow normal serial communications. PTA1 = 1
allows parallel communications during security code entry. (For parallel
communications, configure PTA0 = 0 or PTA0 = 1.)
The MCU initially comes out of reset using the external clock for its clock
source. This overrides the user mode operation of the oscillator circuits
where the part comes up using the internally generated oscillator.
Running from an external clock allows the MCU, using an appropriate
frequency clock source, to communicate with host software at standard
baud rates.
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 — Rev. 1.0
MOTOROLA
Monitor ROM (MON)
Technical Data
257