MC68HC908KX8 Datasheet, PDF (249/310 Pages) Motorola, Inc – Microcontrollers

Analog-to-Digital Converter (ADC)
Interrupts
17.5 Interrupts
When the AIEN bit is set, the ADC module is capable of generating a
CPU interrupt after each ADC conversion. A CPU interrupt is generated
if the COCO bit (ADC status control register, $003C) is at logic 0. If the
COCO bit is set, a direct-memory access (DMA) interrupt is generated.
NOTE: Because the MC68HC908KX8 does not have a DMA module, the COCO
bit should not be set while interrupts are enabled (AIEN = 1).
The COCO bit is not used as a conversion complete flag when interrupts
are enabled.
17.6 Low-Power Modes
The following subsections describe the low-power modes.
17.6.1 Wait Mode
The ADC continues normal operation during wait mode. Any enabled
CPU interrupt request from the ADC can bring the MCU out of wait
mode. If the ADC is not required to bring the MCU out of wait mode,
power down the ADC by setting the ADCH[4:0] bits in the ADC status
and control register before executing the WAIT instruction.
17.6.2 Stop Mode
The ADC module is inactive after the execution of a STOP instruction.
Any pending conversion is aborted. ADC conversions resume when the
MCU exits stop mode. Allow one conversion cycle to stabilize the analog
circuitry before attempting a new ADC conversion after exiting stop
mode.
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 — Rev. 1.0
MOTOROLA
Analog-to-Digital Converter (ADC)
Technical Data
249