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MC68HC908KX8 Datasheet, PDF (64/310 Pages) Motorola, Inc – Microcontrollers
Central Processor Unit (CPU)
5.4.5 Condition Code Register
The 8-bit condition code register (CCR) contains the interrupt mask and
five flags that indicate the results of the instruction just executed. Bits 6
and 5 are set permanently to logic 1. The following paragraphs describe
the functions of the condition code register.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
V
1
1
H
I
N
Z
C
Write:
Reset: X
1
1
X
1
X
X
X
X = Indeterminate
Figure 5-6. Condition Code Register (CCR)
V — Overflow Flag
The CPU sets the overflow flag when a two's complement overflow
occurs. The signed branch instructions BGT, BGE, BLE, and BLT use
the overflow flag.
1 = Overflow
0 = No overflow
H — Half-Carry Flag
The CPU sets the half-carry flag when a carry occurs between
accumulator bits 3 and 4 during an add-without-carry (ADD) or add-
with-carry (ADC) operation. The half-carry flag is required for binary-
coded decimal (BCD) arithmetic operations. The DAA instruction
uses the states of the H and C flags to determine the appropriate
correction factor.
1 = Carry between bits 3 and 4
0 = No carry between bits 3 and 4
I — Interrupt Mask Bit
When the interrupt mask is set, all maskable CPU interrupts are
disabled. CPU interrupts are enabled when the interrupt mask is
cleared. When a CPU interrupt occurs, the interrupt mask is set
automatically after the CPU registers are saved on the stack, but
before the interrupt vector is fetched.
1 = Interrupts disabled
0 = Interrupts enabled
Technical Data
64
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 — Rev. 1.0
Central Processor Unit (CPU)
MOTOROLA