MC68HC908KX8 Datasheet, PDF (119/310 Pages) Motorola, Inc – Microcontrollers

Internal Clock Generator Module (ICG)
Usage Notes
7.5.4 Quantization Error in DCO Output
The digitally controlled oscillator (DCO) is comprised of three major sub-
blocks:
1. Binary weighted divider
2. Variable-delay ring oscillator
3. Ring oscillator fine-adjust circuit
Each of these blocks affects the clock period of the internal clock (ICLK).
Since these blocks are controlled by the digital loop filter (DLF) outputs
DDIV and DSTG, the output of the DCO can change only in quantized
steps as the DLF increments or decrements its output. The following
sections describe how each block will affect the output frequency.
7.5.4.1 Digitally Controlled Oscillator
The digitally controlled oscillator (DCO) is an inaccurate oscillator which
generates the internal clock (ICLK), whose clock period is dependent on
the digital loop filter outputs (DSTG[7:0] and DDIV[3:0]). Because of the
digital nature of the DCO, the clock period of ICLK will change in
quantized steps. This will create a clock period difference or quantization
error (Q-ERR) from one cycle to the next. Over several cycles or for
longer periods, this error is divided out until it reaches a minimum error
of 0.202 percent to 0.368 percent. The dependence of this error on the
DDIV[3:0] value and the number of cycles the error is measured over is
shown in Table 7-2.
Table 7-2. Quantization Error in ICLK
DDIV[3:0]
%0000 (min)
%0000 (min)
%0000 (min)
%0001
%0001
%0001
ICLK Cycles
1
4
≥ 32
1
4
≥ 16
Bus Cycles
NA
1
≥8
NA
1
≥4
τ_ICLK Q-ERR
6.45%–11.8%
1.61%–2.94%
0.202%–0.368%
3.23%–5.88%
0.806%–1.47%
0.202%–0.368%
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 — Rev. 1.0
MOTOROLA
Internal Clock Generator Module (ICG)
Technical Data
119