MC68HC908KX8 Datasheet, PDF (81/310 Pages) Motorola, Inc – Microcontrollers

System Integration Module (SIM)
SIM Bus Clock Control and Generation
6.3 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and
peripherals on the MCU. The system clocks are generated from an
incoming clock, CGMOUT, as shown in Figure 6-3. This clock originates
from either an external oscillator or from the internal clock generator.
ECLK
ICLK
ICG
*(1(5$725
SELECT
CIRCUIT
÷2
CS
MONITOR MODE
USER MODE
ICG
CGMXCLK
A
CGMOUT
B _S*
*:+(1 S = 1,
CGMOUT = B
SIM COUNTER
÷2
BUS CLOCK
GENERATORS
SIM
Figure 6-3. System Clock Signals
6.3.1 Bus Timing
In user mode, the internal bus frequency is the internal clock generator
output (CGMXCLK) divided by four.
6.3.2 Clock Startup from POR or LVI Reset
When the power-on reset (POR) module or the low-voltage inhibit (LVI)
module generates a reset, the clocks to the CPU and peripherals are
inactive and held in an inactive phase until after 4096 CGMXCLK cycles.
The MCU is held in reset by the SIM during this entire period. The bus
clocks start upon completion of the timeout.
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 — Rev. 1.0
MOTOROLA
System Integration Module (SIM)
Technical Data
81