MC68HC908KX8 Datasheet, PDF (39/310 Pages) Motorola, Inc – Microcontrollers

Memory Map
I/O Registers
2.3 I/O Registers
Most of the control, status, and data registers are in the zero-page area
of $0000–$003F. Additional input/output (I/O) registers have the
following addresses:
• $FE01 — SIM reset status register, SRSR
• $FE04 — Interrupt status register 1, INT1
• $FE05 — Interrupt status register 2, INT2
• $FE06 — Interrupt status register 3, INT3
• $FE08 — FLASH control register, FLCR
• $FE09 — Break address register high, BRKH
• $FE0A — Break address register low, BRKL
• $FE0B — Break status and control register, BRKSCR
• $FE0C — LVI status register, LVISR
• $FF7E — FLASH block protect register, FLBPR
in non-volatile FLASH memory
• $FFFF — COP control register, COPCTL
A summary of the registers available on the MC68HC908KX8 is
provided in Figure 2-2. Table 2-1 is a list of vector locations.
Addr.
$0000
$0001
$0002
Register Name
Bit 7
Port A Data Register ^{Read: 0}
(PTA) Write:
See page 151. _Reset:
Port B Data Register ^Read:
(PTB) Write:
See page 155. _Reset:
PTB7
Unimplemented
6
0
PTB6
5
4
3
2
0
PTA4 PTA3 PTA2
Unaffected by reset
PTB5 PTB4 PTB3 PTB2
Unaffected by reset
1
PTA1
PTB1
Bit 0
PTA0
PTB0
= Unimplemented
R = Reserved
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 7)
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 — Rev. 1.0
MOTOROLA
Memory Map
Technical Data
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