MC68HC908KX8 Datasheet, PDF (85/310 Pages) Motorola, Inc – Microcontrollers

System Integration Module (SIM)
Reset and System Initialization
6.4.1.2 Computer Operating Properly (COP) Reset
An input to the SIM is reserved for the COP reset signal. The overflow of
the COP counter causes an internal reset and sets the COP bit in the
reset status register (SRSR).
To prevent a COP module timeout, write any value to location $FFFF.
Writing to location $FFFF clears the COP counter and stages 12–5 of the
SIM counter. The SIM counter output, which occurs at least every
2¹²â€“2⁴ CGMXCLK cycles, drives the COP counter. The COP should be
serviced as soon as possible out of reset to guarantee the maximum
amount of time before the first timeout.
The COP module is disabled if the IRQ1 pin is held at V_TST while the
MCU is in monitor mode. The COP module can be disabled only through
combinational logic conditioned with the high-voltage signal on the IRQ1
pin. This prevents the COP from becoming disabled as a result of
external noise.
6.4.1.3 Illegal Opcode Reset
The SIM decodes signals from the CPU to detect illegal instructions. An
illegal instruction sets the ILOP bit in the SIM reset status register
(SRSR) and causes a reset.
If the stop enable bit, STOP, in the configuration register (CONFIG1) is
logic 0, the SIM treats the STOP instruction as an illegal opcode and
causes an illegal opcode reset.
6.4.1.4 Illegal Address Reset
An opcode fetch from an unmapped address generates an illegal
address reset. The SIM verifies that the CPU is fetching an opcode prior
to asserting the ILAD bit in the SIM reset status register (SRSR) and
resetting the MCU. A data fetch from an unmapped address does not
generate a reset.
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 — Rev. 1.0
MOTOROLA
System Integration Module (SIM)
Technical Data
85