MC68HC908KX8 Datasheet, PDF (134/310 Pages) Motorola, Inc – Microcontrollers

Internal Clock Generator Module (ICG)
7.8.3 ICG Trim Register
Address: $0038
Bit 7
6
5
4
3
2
1
Read:
TRIM7
Write:
TRIM6
TRIM5
TRIM4
TRIM3
TRIM2
TRIM1
Reset: 1
0
0
0
0
0
0
Figure 7-13. ICG Trim Register (ICGTR)
Bit 0
TRIM0
0
TRIM7:TRIM0 — ICG Trim Factor Bits
These read/write bits change the size of the internal capacitor used
by the internal clock generator. By testing the frequency of the internal
clock and incrementing or decrementing this factor accordingly, the
accuracy of the internal clock can be improved per electrical
specifications found in 20.10 Trimmed Accuracy of the Internal
Clock Generator. Incrementing this register by one decreases the
frequency by 0.195 percent of the unadjusted value. Decrementing
this register by one increases the frequency by 0.195 percent. This
register cannot be written when the CMON bit is set. Reset sets these
bits to $80, centering the range of possible adjustment.
7.8.4 ICG DCO Divider Register
Address: $0039
Bit 7
6
5
4
3
2
1
Bit 0
Read:
DDIV3 DDIV2 DDIV1 DDIV0
Write:
Reset: 0
0
0
0
U
U
U
U
= Unimplemented
U = Unaffected
Figure 7-14. ICG DCO Divider Control Register (ICGDVR)
DDIV3:DDIV0 — ICG DCO Divider Control Bits
These bits indicate the number of divide-by-twos (DDIV) that follow
the digitally controlled oscillator. When ICGON is set, DDIV is
controlled by the digital loop filter. The range of valid values for DDIV
Technical Data
134
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 — Rev. 1.0
Internal Clock Generator Module (ICG)
MOTOROLA