MC68HC908KX8 Datasheet, PDF (82/310 Pages) Motorola, Inc – Microcontrollers

System Integration Module (SIM)
6.3.3 Clocks in Stop Mode and Wait Mode
Upon exit from stop mode by an interrupt or reset, the SIM allows
CGMXCLK to clock the SIM counter. The CPU and peripheral clocks do
not become active until after the stop delay timeout. Stop mode recovery
timing is discussed in detail in 6.7.2 Stop Mode.
In wait mode, the CPU clocks are inactive. Refer to the wait mode
subsection of each module to see if the module is active or inactive in
wait mode. Some modules can be programmed to be active in wait
mode.
6.4 Reset and System Initialization
The MCU has these internal reset sources:
• Power-on reset (POR) module
• Computer operating properly (COP) module
• Low-voltage inhibit (LVI) module
• Illegal opcode
• Illegal address
• Forced monitor mode entry reset (MENRST) module
All of these resets produce the vector $FFFE–$FFFF ($FEFE–$FEFF in
monitor mode) and assert the internal reset signal (IRST). IRST causes
all registers to be returned to their default values and all modules to be
returned to their reset states.
These internal resets clear the SIM counter and set a corresponding bit
in the SIM reset status register (SRSR). See 6.5 SIM Counter and
6.8.1 SIM Reset Status Register.
Technical Data
82
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 — Rev. 1.0
System Integration Module (SIM)
MOTOROLA