MC68HC908KX8 Datasheet, PDF (234/310 Pages) Motorola, Inc – Microcontrollers

Timer Interface Module (TIM)
16.6.1 Wait Mode
The TIM remains active after the execution of a WAIT instruction. In wait
mode the TIM registers are not accessible by the CPU. Any enabled
CPU interrupt request from the TIM can bring the MCU out of wait mode.
If TIM functions are not required during wait mode, reduce power
consumption by stopping the TIM before executing the WAIT instruction.
16.6.2 Stop Mode
The TIM is inactive after the execution of a STOP instruction. The STOP
instruction does not affect register conditions or the state of the TIM
counter. TIM operation resumes when the MCU exits stop mode after an
external interrupt.
16.7 I/O Signals
Port A shares two of its pins with the TIM, PTA3/KBD3/TCH1and
PTA2/KBD2/TCH0. Each channel input/output (I/O) pin is
programmable independently as an input capture pin or an output
compare pin. TCH0 can be configured as buffered output compare or
buffered PWM pins.
16.8 I/O Registers
These I/O registers control and monitor operation of the TIM:
• TIM status and control register (TSC)
• TIM control registers (TCNTH and TCNTL)
• TIM counter modulo registers (TMODH and TMODL)
• TIM channel status and control registers (TSC0 and TSC1)
• TIM channel registers (TCH0H and TCH0L, TCH1H and TCH1L)
Technical Data
234
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 — Rev. 1.0
Timer Interface Module (TIM)
MOTOROLA