MC68HC908KX8 Datasheet, PDF (220/310 Pages) Motorola, Inc – Microcontrollers

Timebase Module (TBM)
15.8 Timebase Control Register
The timebase has one register, the timebase control register (TBCR),
which is used to enable the timebase interrupts and set the rate.
Address: $001C
Bit 7
6
5
4
3
2
1
Bit 0
Read: TBIF
0
TBR2 TBR1 TBR0
TBIE TBON
R
Write:
TACK
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
R = Reserved
Figure 15-2. Timebase Control Register (TBCR)
TBIF — Timebase Interrupt Flag
This read-only flag bit is set when the timebase counter has rolled
over.
1 = Timebase interrupt pending
0 = Timebase interrupt not pending
TBR2–TBR0 — Timebase Divider Selection Bits
These read/write bits select the tap in the counter to be used for
timebase interrupts as shown in Table 15-1.
NOTE: Do not change TBR2–TBR0 bits while the timebase is enabled
(TBON = 1).
TACK— Timebase ACKnowledge Bit
The TACK bit is a write-only bit and always reads as 0. Writing a
logic 1 to this bit clears TBIF, the timebase interrupt flag bit. Writing a
logic 0 to this bit has no effect.
1 = Clear timebase interrupt flag
0 = No effect
TBIE — Timebase Interrupt Enabled Bit
This read/write bit enables the timebase interrupt when the TBIF bit
becomes set. Reset clears the TBIE bit.
1 = Timebase interrupt is enabled.
0 = Timebase interrupt is disabled.
Technical Data
220
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 — Rev. 1.0
Timebase Module (TBM)
MOTOROLA