MC68HC908KX8 Datasheet, PDF (275/310 Pages) Motorola, Inc – Microcontrollers

Break (BRK) Module
Break Module Registers
19.6.3 Break Status Register
The break status register (SBSR) contains a flag to indicate that a break
caused an exit from wait mode. The flag is useful in applications
requiring a return to wait mode after exiting from a break interrupt.
Address: $FE00
Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
0
0
1
0
0
BW
0
Write: R
R
R
R
R
R
NOTE
R
Reset: 0
0
0
1
0
0
0
0
Note: Writing a logic 0 clears BW.
R = Reserved
Figure 19-6. SIM Break Status Register (SBSR)
BW — Break Wait Bit
This read/write bit is set when a break interrupt causes an exit from
wait mode. Clear BW by writing a logic 0 to it. Reset clears BW.
1 = Break interrupt during wait mode
0 = No break interrupt during wait mode
BW can be read within the break interrupt routine. The user can modify
the return address on the stack by subtracting 1 from it. The following
code is an example.
This code works if the H register was stacked in the break interrupt
routine. Execute this code at the end of the break interrupt routine.
HIBYTE
LOBYTE
DOLO
RETURN
EQU
EQU
BRCLR
TST
BNE
DEC
DEC
PULH
RTI
5
6
BW,BSR, RETURN
LOBYTE,SP
DOLO
HIBYTE,SP
LOBYTE,SP
; If not BW, do RTI
; See if wait mode or stop mode
; was exited by break.
; If RETURNLO is not 0,
; then just decrement low byte.
; Else deal with high byte also.
; Point to WAIT/STOP opcode.
; Restore H register.
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 — Rev. 1.0
MOTOROLA
Break (BRK) Module
Technical Data
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