MC68HC908KX8 Datasheet, PDF (112/310 Pages) Motorola, Inc – Microcontrollers

Internal Clock Generator Module (ICG)
7.4.4.3 External Clock Activity Detector
The external clock activity detector, shown in Figure 7-6, looks for at
least one falling edge on the external clock (ECLK) every time the
internal reference (IREF) is low. Since IREF is less than half the
frequency of ECLK, this should occur every time. If it does not occur two
consecutive times, the external clock inactivity indicator (EOFF) is set.
EOFF will be cleared the next time there is a falling edge of ECLK while
IREF is low.
The external clock stable bit (ECGS) is also generated in the external
clock activity detector. ECGS is set on a falling edge of the external
stabilization clock (ESTBCLK). This will be 4096 ECLK cycles after the
external clock generator on bit is set, or the MCU exits stop mode
(ECGEN = 1) if the external crystal enable (EXTXTALEN) in the
CONFIG or MOR is set, or 16 cycles when EXTXTALEN is clear. ECGS
is cleared when the external clock generator is turned off or in stop mode
(ECGEN is clear) or when EOFF is set.
CMON
IREF
ECLK
ESTBCLK
ECGEN
R
D
DFFRS
CK Q
S
CK Q
1/4
R
R
D
DFFRR
CK Q
R
EOFF
EGGS
NAME
NAME
CONFIGURATION (OR MOR) REGISTER BIT
TOP LEVEL SIGNAL
NAME
NAME
REGISTER BIT
MODULE SIGNAL
Figure 7-6. External Clock Activity Detector
Technical Data
112
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 — Rev. 1.0
Internal Clock Generator Module (ICG)
MOTOROLA