MC68HC908KX8 Datasheet, PDF (166/310 Pages) Motorola, Inc – Microcontrollers

External Interrupt (IRQ)
12.4 Functional Description
A logic 0 applied to the external interrupt pin can latch a central
processor unit (CPU) interrupt request. Figure 12-1 shows the structure
of the IRQ module.
Interrupt signals on the IRQ1 pin are latched into the IRQ1 latch. An
interrupt latch remains set until one of these actions occurs:
• Vector fetch — A vector fetch automatically generates an interrupt
acknowledge signal that clears the latch that caused the vector
fetch.
• Software clear — Software can clear an interrupt latch by writing
to the appropriate acknowledge bit in the interrupt status and
control register (ISCR). Writing a logic 1 to the ACK1 bit clears the
IRQ1 latch.
• Reset — A reset automatically clears the interrupt latch.
The external interrupt pin is falling-edge triggered and is software-
configurable to be both falling-edge and low-level triggered. The MODE1
bit in the ISCR controls the triggering sensitivity of the IRQ1 pin.
ACK1
VECTOR
FETCH
DECODER
V_''
INTERNAL
PULLUP
DEVICE
IRQ1
V_''
D ^CLR Q
CK
IRQ1
LATCH
SYNCHRONIZER
IMASK1
TO CPU FOR
BIL/BIH
INSTRUCTIONS
IRQF1
IRQ1
INTERRUPT
REQUEST
Technical Data
166
MODE1
HIGH
VOLTAGE
DETECT
Figure 12-1. IRQ Block Diagram
TO MODE
SELECT
LOGIC
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 — Rev. 1.0
External Interrupt (IRQ)
MOTOROLA