MC68HC908KX8 Datasheet, PDF (139/310 Pages) Motorola, Inc – Microcontrollers

Low-Voltage Inhibit (LVI)
Functional Description
Once an LVI reset occurs, the MCU remains in reset until V_DD rises
above a voltage, V_TRIPR, which causes the MCU to exit reset. See
Section 6. System Integration Module (SIM) for the reset recovery
sequence.
The output of the comparator controls the state of the LVIOUT flag in the
LVI status register (LVISR) and can be used for polling LVI operation
when the LVI reset is disabled.
V_DD
STOP INSTRUCTION
LOW V_DD
DETECTOR
LVIPWRD
FROM CONFIG
V_DD > LVITRIP = 0
V_DD ≤ LVITRIP = 1
LVI5OR3
FROM CONFIG
FROM CONFIG
LVIRSTD
LVIOUT
LVISTOP
FROM CONFIG
LVI RESET
Figure 8-1. LVI Module Block Diagram
8.4.1 Polled LVI Operation
In applications that can operate at V_DD levels below the V_TRIPF level,
software can monitor V_DD by polling the LVIOUT bit. In the configuration
register, the LVIPWRD bit must be at logic 0 to enable the LVI module,
and the LVIRSTD bit must be at logic 1 to disable LVI resets.
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 — Rev. 1.0
MOTOROLA
Low-Voltage Inhibit (LVI)
Technical Data
139