MC68HC908KX8 Datasheet, PDF (141/310 Pages) Motorola, Inc – Microcontrollers

Low-Voltage Inhibit (LVI)
LVI Status Register
8.5 LVI Status Register
The LVI status register (LVISR) indicates if the V_DD voltage was detected
below the V_TRIPF level while LVI resets have been disabled.
Address: $FE0C
Bit 7
6
5
4
3
2
1
Bit 0
Read: LVIOUT
0
0
0
0
0
0
R
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
R = Reserved
Figure 8-2. LVI Status Register (LVISR)
LVIOUT — LVI Output Bit
This read-only flag becomes set when the V_DD voltage falls below the
V_TRIPF trip voltage and is cleared when V_DD voltage rises above V_TRIPR.
The difference in these threshold levels results in a hysteresis that
prevents oscillation into and out of reset. (See Table 8-1.) Reset
clears the LVIOUT bit.
Table 8-1. LVIOUT Bit Indication
V_DD
V_DD > V_TRIPR
V_DD < V_TRIPF
V_TRIPF < V_DD < V_TRIPR
LVIOUT
0
1
Previous value
8.6 LVI Interrupts
The LVI module does not generate interrupt requests.
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 — Rev. 1.0
MOTOROLA
Low-Voltage Inhibit (LVI)
Technical Data
141