MC68HC908KX8 Datasheet, PDF (147/310 Pages) Motorola, Inc – Microcontrollers

Configuration Register (CONFIG)
Functional Description
SCIBDSRC — SCI Baud Rate Clock Source Bit
SCIBDSRC controls the clock source used for the SCI. The setting of
this bit affects the frequency at which the SCI operates.
1 = Internal data bus clock is used as clock source for SCI.
0 = CGMXCLK is used as clock source for SCI.
COPRS — COP Rate Select Bit
COPD selects the COP timeout period. Reset clears COPRS. See
Section 11. Computer Operating Properly Module (COP).
1 = COP timeout period = 2¹³ – 2⁴ CGMXCLK cycles
0 = COP timeout period = 2¹⁸ – 2⁴ CGMXCLK cycles
LVISTOP — LVI Enable in Stop Mode Bit
When the LVIPWRD bit is clear, setting the LVISTOP bit enables the
LVI to operate during stop mode. Reset clears LVISTOP.
1 = LVI enabled during stop mode
0 = LVI disabled during stop mode
LVIRSTD — LVI Reset Disable Bit
LVIRSTD disables the reset signal from the LVI module.
See Section 8. Low-Voltage Inhibit (LVI).
1 = LVI module resets disabled
0 = LVI module resets enabled
LVIPWRD — LVI Power Disable Bit
LVIPWRD disables the LVI module. See Section 8. Low-Voltage
Inhibit (LVI).
1 = LVI module power disabled
0 = LVI module power enabled
LVI5OR3 — LVI 5-V or 3-V Operating Mode Bit
LVI5OR3 selects the voltage operating mode of the LVI module. See
Section 8. Low-Voltage Inhibit (LVI). The voltage mode selected for
the LVI should match the operating V_DD. See Section 20. Electrical
Specifications for the LVI’s voltage trip points for each of the modes.
1 = LVI operates in 5-V mode.
0 = LVI operates in 3-V mode.
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 — Rev. 1.0
MOTOROLA
Configuration Register (CONFIG)
Technical Data
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