MC68HC908KX8 Datasheet, PDF (110/310 Pages) Motorola, Inc – Microcontrollers

Internal Clock Generator Module (ICG)
7.4.4.1 Clock Monitor Reference Generator
The clock monitor uses a reference based on one clock source to
monitor the other clock source. The clock monitor reference generator
generates the external reference clock (EREF) based on the external
clock (ECLK) and the internal reference clock (IREF) based on the
internal clock (ICLK). To simplify the circuit, the low-frequency base
clock (IBASE) is used in place of ICLK because it always operates at or
near 307.2 kHz. For proper operation, EREF must be at least twice as
slow as IBASE and IREF must be at least twice as slow as ECLK.
To guarantee that IREF is slower than ECLK and EREF is slower than
IBASE, one of the signals is divided down. Which signal is divided and
by how much is determined by the external slow (EXTSLOW) and
external crystal enable (EXTXTALEN) bits in the CONFIG or MOR,
according to the rules in Table 7-2.
NOTE: Each signal (IBASE and ECLK) is always divided by four. A longer
divider is used on either IBASE or ECLK based on the EXTSLOW bit.
To conserve size, the long divider (divide by 4096) is also used as an
external crystal stabilization divider. The divider is reset when the
external clock generator is turned off or in stop mode (ECGEN is clear).
When the external clock generator is first turned on, the external clock
generator stable bit (ECGS) will be clear. This condition automatically
selects ECLK as the input to the long divider. The external stabilization
clock (ESTBCLK) will be ECLK divided by 16 when EXTXTALEN is low
or 4096 when EXTXTALEN is high. This timeout allows the crystal to
stabilize. The falling edge of ESTBCLK is used to set ECGS, which will
set after a full 16 or 4096 cycles. When ECGS is set, the divider returns
to its normal function. ESTBCLK may be generated by either IBASE or
ECLK, but any clocking will only reinforce the set condition. If ECGS is
cleared because the clock monitor determined that ECLK was inactive,
the divider will revert to a stabilization divider. Since this will change the
EREF and IREF divide ratios, it is important to turn the clock monitor off
(CMON = 0) after inactivity is detected to ensure valid recovery.
Technical Data
110
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 — Rev. 1.0
Internal Clock Generator Module (ICG)
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