MC68HC908KX8 Datasheet, PDF (168/310 Pages) Motorola, Inc – Microcontrollers

External Interrupt (IRQ)
latches another interrupt request. If the IRQ1 mask bit, IMASK1, is
clear, the CPU loads the program counter with the vector address
at locations $FFFA and $FFFB.
• Return of the IRQ1 pin to logic 1 — As long as the IRQ1 pin is at
logic 0, the IRQ1 latch remains set.
The vector fetch or software clear and the return of the IRQ1 pin to
logic 1 can occur in any order. The interrupt request remains pending as
long as the IRQ1 pin is at logic 0. A reset will clear the latch and the
MODE1 control bit, thereby clearing the interrupt even if the pin stays
low.
If the MODE1 bit is clear, the IRQ1 pin is falling-edge sensitive only. With
MODE1 clear, a vector fetch or software clear immediately clears the
IRQ1 latch.
The IRQF1 bit in the ISCR can be used to check for pending interrupts.
The IRQF1 bit is not affected by the IMASK1 bit, which makes it useful
in applications where polling is preferred.
Use the branch if interrupt pin is high (BIH) or branch if interrupt pin is
low (BIL) instruction to read the logic level on the IRQ1 pin.
NOTE: When using the level-sensitive interrupt trigger, avoid false interrupts by
masking interrupt requests in the interrupt routine.
12.6 IRQ Status and Control Register
The IRQ status and control register (ISCR) controls and monitors
operation of the IRQ module. The ISCR has these functions:
• Shows the state of the IRQ1 interrupt flag
• Clears the IRQ1 interrupt latch
• Masks IRQ1 interrupt request
• Controls triggering sensitivity of the IRQ1 interrupt pin
Technical Data
168
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 — Rev. 1.0
External Interrupt (IRQ)
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