MC68HC908KX8 Datasheet, PDF (148/310 Pages) Motorola, Inc – Microcontrollers

Configuration Register (CONFIG)
NOTE: The LVI5OR3 bit is cleared by a power-on reset (POR) only. Other
resets will leave this bit unaffected.
SSREC — Short Stop Recovery Bit
SSREC enables the CPU to exit stop mode with a delay of 32
CGMXCLK cycles instead of a 4096-CGMXCLK cycle delay.
1 = Stop mode recovery after 32 CGMXCLK cycles
0 = Stop mode recovery after 4096 CGMXCLCK cycles
NOTE: Exiting stop mode by an LVI reset will result in the long stop recovery.
If the system clock source selected is the internal oscillator or the
external crystal and the OSCENINSTOP configuration bit is not set,
the oscillator will be disabled during stop mode. The short stop
recovery does not provide enough time for oscillator stabilization and
thus the SSREC bit should not be set.
When using the LVI during normal operation but disabling during stop
mode, the LVI will have an enable time of t_EN. The system
stabilization time for power-on reset and long stop recovery (both
4096 CGMXCLK cycles) gives a delay longer than the LVI enable
time for these startup scenarios. There is no period where the MCU is
not protected from a low-power condition. However, when using the
short stop recovery configuration option, the 32-CGMXCLK delay
must be greater than the LVI’s turn on time to avoid a period in startup
where the LVI is not protecting the MCU.
STOP — STOP Instruction Enable Bit
STOP enables the STOP instruction.
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
COPD — COP Disable Bit
COPD disables the COP module. See Section 11. Computer
Operating Properly Module (COP).
1 = COP module disabled
0 = COP module enabled
Technical Data
148
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 — Rev. 1.0
Configuration Register (CONFIG)
MOTOROLA