PIC18F67J11-IPT Datasheet, PDF (91/448 Pages) Microchip Technology – 64/80-Pin High-Performance, 1-Mbit Flash Microcontrollers with nanoWatt Technology

PIC18F87J11 FAMILY
REGISTER 6-1: EECON1: EEPROM CONTROL REGISTER 1
U-0
—
bit 7
U-0
R/W-0
R/W-0
R/W-x
R/W-0
—
WPROG
FREE
WRERR⁽¹⁾
WREN
R/S-0
WR
U-0
—
bit 0
Legend:
R = Readable bit
-n = Value at POR
S = Set-only bit (cannot be cleared in software)
W = Writable bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Unimplemented: Read as ‘0’
WPROG: One Word-Wide Program bit
1 = Program 2 bytes on the next WR command
0 = Program 64 bytes on the next WR command
FREE: Flash Row Erase Enable bit
1 = Erase the program memory row addressed by TBLPTR on the next WR command
(cleared by completion of erase operation)
0 = Perform write only
WRERR: Flash Program Error Flag bit⁽¹⁾
1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal
operation, or an improper write attempt)
0 = The write operation completed
WREN: Flash Program Write Enable bit
1 = Allows write cycles to Flash program memory
0 = Inhibits write cycles to Flash program memory
WR: Write Control bit
1 = Initiates a program memory erase cycle or write cycle
(The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit
can only be set (not cleared) in software.)
0 = Write cycle is complete
Unimplemented: Read as ‘0’
Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error
condition.
© 2009 Microchip Technology Inc.
DS39778D-page 91