PIC18F67J11-IPT Datasheet, PDF (26/448 Pages) Microchip Technology – 64/80-Pin High-Performance, 1-Mbit Flash Microcontrollers with nanoWatt Technology

PIC18F87J11 FAMILY
TABLE 1-4: PIC18F8XJ1X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number _{Pin Buffer}
80-TQFP ^{Type Type}
Description
PORTD is a bidirectional I/O port.
RD0/AD0/PMD0
RD0
AD0
PMD0⁽⁶⁾
72
I/O ST
Digital I/O.
I/O TTL
External memory address/data 0.
I/O TTL
Parallel Master Port data.
RD1/AD1/PMD1
RD1
AD1
PMD1⁽⁶⁾
69
I/O ST
Digital I/O.
I/O TTL
External memory address/data 1.
I/O TTL
Parallel Master Port data.
RD2/AD2/PMD2
RD2
AD2
PMD2⁽⁶⁾
68
I/O ST
Digital I/O.
I/O TTL
External memory address/data 2.
I/O TTL
Parallel Master Port data.
RD3/AD3/PMD3
RD3
AD3
PMD3⁽⁶⁾
67
I/O ST
Digital I/O.
I/O TTL
External memory address/data 3.
I/O TTL
Parallel Master Port data.
RD4/AD4/PMD4/SDO2
RD4
AD4
PMD4⁽⁶⁾
SDO2
66
I/O ST
Digital I/O.
I/O TTL
External memory address/data 4.
I/O TTL
Parallel Master Port data.
O
—
SPI data out.
RD5/AD5/PMD5/
SDI2/SDA2
RD5
AD5
PMD5⁽⁶⁾
SDI2
SDA2
65
I/O ST
I/O TTL
I/O TTL
I
ST
I/O ST
Digital I/O.
External memory address/data 5.
Parallel Master Port data.
SPI data in.
I²C™ data I/O.
RD6/AD6/PMD6/
SCK2/SCL2
RD6
AD6
PMD6⁽⁶⁾
SCK2
SCL2
64
I/O ST
I/O TTL
I/O TTL
I/O ST
I/O ST
Digital I/O.
External memory address/data 6.
Parallel Master Port data.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I²C mode.
RD7/AD7/PMD7/SS2
RD7
AD7
PMD7⁽⁶⁾
SS2
63
I/O ST
Digital I/O.
I/O TTL
External memory address/data 7.
I/O TTL
Parallel Master Port data.
I
TTL
SPI slave select input.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I = Input
O
= Output
P = Power
OD = Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared (Extended Microcontroller mode).
2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set).
3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode).
5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).
6: Default assignment for PMP data and control pins when PMPMX Configuration bit is set.
7: Alternate assignment for PMP data and control pins when PMPMX Configuration bit is cleared (programmed).
DS39778D-page 26
© 2009 Microchip Technology Inc.