PIC18F67J11-IPT Datasheet, PDF (42/448 Pages) Microchip Technology – 64/80-Pin High-Performance, 1-Mbit Flash Microcontrollers with nanoWatt Technology

PIC18F87J11 FAMILY
2.7 Effects of Power-Managed Modes
on the Various Clock Sources
When PRI_IDLE mode is selected, the designated pri-
mary oscillator continues to run without interruption.
For all other power-managed modes, the oscillator
using the OSC1 pin is disabled. The OSC1 pin (and
OSC2 pin if used by the oscillator) will stop oscillating.
In secondary clock modes (SEC_RUN and
SEC_IDLE), the Timer1 oscillator is operating and
providing the device clock. The Timer1 oscillator may
also run in all power-managed modes if required to
clock Timer1 or Timer3.
In RC_RUN and RC_IDLE modes, the internal
oscillator provides the device clock source. The 31 kHz
INTRC output can be used directly to provide the clock
and may be enabled to support various special
features, regardless of the power-managed mode (see
Section 24.2 “Watchdog Timer (WDT)” through
Section 24.5 “Fail-Safe Clock Monitor” for more
information on WDT, Fail-Safe Clock Monitor and
Two-Speed Start-up).
If the Sleep mode is selected, all clock sources are
stopped. Since all the transistor switching currents
have been stopped, Sleep mode achieves the lowest
current consumption of the device (only leakage
currents).
Enabling any on-chip feature that will operate during
Sleep will increase the current consumed during Sleep.
The INTRC is required to support WDT operation. The
Timer1 oscillator may be operating to support a Real-
Time Clock (RTC). Other features may be operating
that do not require a device clock source (i.e., MSSP
slave, PSP, INTx pins and others). Peripherals that
may add significant current consumption are listed in
Section 27.2 “DC Characteristics: Power-Down and
Supply Current”.
2.8 Power-up Delays
Power-up delays are controlled by two timers, so that
no external Reset circuitry is required for most applica-
tions. The delays ensure that the device is kept in
Reset until the device power supply is stable under nor-
mal circumstances and the primary clock is operating
and stable. For additional information on power-up
delays, see Section 4.6 “Power-up Timer (PWRT)”.
The first timer is the Power-up Timer (PWRT), which
provides a fixed delay on power-up (parameter 33,
Table 27-12); it is always enabled.
The second timer is the Oscillator Start-up Timer
(OST), intended to keep the chip in Reset until the
crystal oscillator is stable (HS modes). The OST does
this by counting 1024 oscillator cycles before allowing
the oscillator to clock the device.
There is a delay of interval TCSD (parameter 38,
Table 27-12), following POR, while the controller
becomes ready to execute instructions.
TABLE 2-3: OSC1 AND OSC2 PIN STATES IN SLEEP MODE
Oscillator Mode
OSC1 Pin
OSC2 Pin
EC, ECPLL
HS, HSPLL
INTOSC, INTPLL1/2
Floating, pulled by external clock
Feedback inverter disabled at quiescent
voltage level
I/O pin RA6, direction controlled by
TRISA<6>
At logic low (clock/4 output)
Feedback inverter disabled at quiescent
voltage level
I/O pin RA6, direction controlled by
TRISA<7>
Note: See Section 4.0 “Reset” for time-outs due to Sleep and MCLR Reset.
DS39778D-page 42
© 2009 Microchip Technology Inc.