PIC18F67J11-IPT Datasheet, PDF (444/448 Pages) Microchip Technology – 64/80-Pin High-Performance, 1-Mbit Flash Microcontrollers with nanoWatt Technology

PIC18F87J11 FAMILY
I²C Slave Mode (7-Bit Reception, SEN = 1) ............ 250
I²C Slave Mode (7-Bit Transmission) ....................... 244
I²C Slave Mode General Call Address Sequence (7 or
10-Bit Addressing Mode) ................................. 252
I²C Stop Condition Receive or Transmit Mode ........ 263
MSSP I²C Bus Data ................................................. 419
MSSP I²C Bus Start/Stop Bits ................................. 419
Parallel Master Port Read ........................................ 410
Parallel Master Port Write ........................................ 411
Parallel Slave Port ................................................... 409
Parallel Slave Port Read .................................. 162, 165
Parallel Slave Port Write .................................. 162, 165
Program Memory Read ............................................ 405
Program Memory Write ............................................ 406
PWM Auto-Shutdown (P1RSEN = 0, Auto-Restart Dis-
abled) ............................................................... 219
PWM Auto-Shutdown (P1RSEN = 1, Auto-Restart En-
abled) ............................................................... 219
PWM Direction Change ........................................... 216
PWM Direction Change at Near 100% Duty Cycle .. 216
PWM Output ............................................................ 202
Read and Write, 8-Bit Data, Demultiplexed Address 169
Read, 16-Bit Data, Demultiplexed Address ............. 172
Read, 16-Bit Muliplexed Data, Fully Multiplexed 16-Bit
Address ............................................................ 174
Read, 16-Bit Multiplexed Data, Partially Multiplexed Ad-
dress ................................................................ 173
Read, 8-Bit Data, Fully Multiplexed 16-Bit Address . 171
Read, 8-Bit Data, Partially Multiplexed Address ...... 169
Read, 8-Bit Data, Partially Multiplexed Address, Enable
Strobe .............................................................. 171
Read, 8-Bit Data, Wait States Enabled, Partially Multi-
plexed Address ................................................ 170
Repeated Start Condition ......................................... 258
Reset, Watchdog Timer (WDT), Oscillator Start-up Timer
(OST) and Power-up Timer (PWRT) ................ 407
Send Break Character Sequence ............................ 286
Slave Synchronization ............................................. 229
Slow Rise Time (MCLR Tied to VDD, VDD Rise > TPWRT)
............................................................................ 55
SPI Mode (Master Mode) ......................................... 228
SPI Mode (Slave Mode, CKE = 0) ........................... 230
SPI Mode (Slave Mode, CKE = 1) ........................... 230
Synchronous Reception (Master Mode, SREN) ...... 289
Synchronous Transmission ...................................... 287
Synchronous Transmission (Through TXEN) .......... 288
Time-out Sequence on Power-up (MCLR Not Tied to
VDD), Case 1 ...................................................... 54
Time-out Sequence on Power-up (MCLR Not Tied to
VDD), Case 2 ...................................................... 55
Time-out Sequence on Power-up (MCLR Tied to VDD,
VDD Rise < TPWRT) ............................................ 54
Timer0 and Timer1 External Clock .......................... 408
Transition for Entry to Idle Mode ................................ 48
Transition for Entry to SEC_RUN Mode .................... 45
Transition for Entry to Sleep Mode ............................ 47
Transition for Two-Speed Start-up (INTRC to HSPLL) ..
326
Transition for Wake From Idle to Run Mode .............. 48
Transition for Wake From Sleep (HSPLL) ................. 47
Transition From RC_RUN Mode to PRI_RUN Mode . 46
Transition From SEC_RUN Mode to PRI_RUN Mode
(HSPLL) ............................................................. 45
Transition to RC_RUN Mode ..................................... 46
Write, 16-Bit Muliplexed Data, Fully Multiplexed 16-Bit
Address ........................................................... 174
Write, 16-Bit Muliplexed Data, Partially Multiplexed Ad-
dress ................................................................ 173
Write, 8-Bit Data, Demultiplexed Address ............... 172
Write, 8-Bit Data, Fully Multiplexed 16-Bit Address . 172
Write, 8-Bit Data, Partially Multiplexed Address ...... 170
Write, 8-Bit Data, Partially Multiplexed Address, Enable
Strobe .............................................................. 171
Write, 8-Bit Data, Wait States Enabled, Partially Multi-
plexed Address ................................................ 170
Timing Diagrams and Specifications
Capture/Compare/PWM Requirements (Including ECCP
Modules) .......................................................... 412
CLKO and I/O Requirements ........................... 404, 405
EUSART Synchronous Receive Requirements ....... 421
EUSART Synchronous Transmission Requirements ....
421
Example SPI Mode Requirements (Master Mode, CKE =
0) ..................................................................... 413
Example SPI Mode Requirements (Master Mode, CKE =
1) ..................................................................... 414
Example SPI Mode Requirements (Slave Mode, CKE =
0) ..................................................................... 415
Example SPI Slave Mode Requirements (CKE = 1) 416
External Clock Requirements .................................. 402
I²C Bus Data Requirements (Slave Mode) .............. 418
I²C Bus Start/Stop Bits Requirements (Slave Mode) .....
417
Internal RC Accuracy (INTOSC, INTRC Sources) ... 403
MSSP I²C Bus Data Requirements ......................... 420
MSSP I²C Bus Start/Stop Bits Requirements .......... 419
Parallel Master Port Read Requirements ................ 410
Parallel Master Port Write ........................................ 411
Parallel Slave Port Requirements ............................ 409
PLL Clock ................................................................ 403
Program Memory Write Requirements .................... 406
Reset, Watchdog Timer (WDT), Oscillator Start-up Timer
(OST), Power-up Timer (PWRT) and Brown-out
Reset ............................................................... 407
Timer0 and Timer1 External Clock Requirements ... 408
TSTFSZ ........................................................................... 371
Two-Speed Start-up ................................................. 315, 326
Two-Word Instructions
Example Cases .......................................................... 71
TXSTAx Register
BRGH Bit ................................................................. 275
V
VDDCORE/VCAP Pin .......................................................... 325
Voltage Reference Specifications .................................... 399
Voltage Regulator (On-Chip) ........................................... 325
Operation in Sleep Mode ......................................... 326
Power-up Requirements .......................................... 326
W
Watchdog Timer (WDT) ........................................... 315, 323
Associated Registers ............................................... 324
Control Register ....................................................... 323
During Oscillator Failure .......................................... 327
Programming Considerations .................................. 323
WCOL ...................................................... 257, 258, 259, 262
WCOL Status Flag ................................... 257, 258, 259, 262
WWW Address ................................................................ 433
WWW, On-Line Support ...................................................... 7
DS39778D-page 444
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