PIC18F67J11-IPT Datasheet, PDF (198/448 Pages) Microchip Technology – 64/80-Pin High-Performance, 1-Mbit Flash Microcontrollers with nanoWatt Technology

PIC18F87J11 FAMILY
17.1 CCP Module Configuration
Each Capture/Compare/PWM module is associated
with a control register (generically, CCPxCON) and a
data register (CCPRx). The data register, in turn, is
comprised of two 8-bit registers: CCPRxL (low byte)
and CCPRxH (high byte). All registers are both
readable and writable.
17.1.1 CCP MODULES AND TIMER
RESOURCES
The ECCP/CCP modules utilize Timers 1, 2, 3 or 4,
depending on the mode selected. Timer1 and Timer3
are available to modules in Capture or Compare
modes, while Timer2 and Timer4 are available for
modules in PWM mode.
TABLE 17-1: CCP MODE – TIMER
RESOURCE
CCP Mode
Timer Resource
Capture
Compare
PWM
Timer1 or Timer3
Timer1 or Timer3
Timer2 or Timer4
The assignment of a particular timer to a module is
determined by the timer to CCP enable bits in the
T3CON register (Register 15-1, page 191). Depending
on the configuration selected, up to four timers may be
active at once, with modules in the same configuration
(Capture/Compare or PWM) sharing timer resources.
The possible configurations are shown in Figure 17-1.
17.1.2 OPEN-DRAIN OUTPUT OPTION
When operating in Output mode (i.e., in Compare or
PWM modes), the drivers for the CCP pins can be
optionally configured as open-drain outputs. This feature
allows the voltage level on the pin to be pulled to a higher
level through an external pull-up resistor, and allows the
output to communicate with external circuits without the
need for additional level shifters. For more information,
see Section 10.1.4 “Open-Drain Outputs”.
The open-drain output option is controlled by the bits in
the ODCON1 register. Setting the appropriate bit con-
figures the pin for the corresponding module for
open-drain operation. The ODCON1 memory shares
the same address space as TMR1H. The ODCON1
register can be accessed by setting the ADSHR bit in
the WDTCON register (WDTCON<4>).
FIGURE 17-1:
ECCPx/CCPx AND TIMER INTERCONNECT CONFIGURATIONS
T3CCP<2:1> = 00
T3CCP<2:1> = 01
T3CCP<2:1> = 10
T3CCP<2:1> = 11
TMR1
TMR3
TMR1
TMR3
TMR1
TMR3
TMR1
TMR3
ECCP1
ECCP2
ECCP3
CCP4
CCP5
ECCP1
ECCP2
ECCP3
CCP4
CCP5
ECCP1
ECCP2
ECCP3
CCP4
CCP5
ECCP1
ECCP2
ECCP3
CCP4
CCP5
TMR2
TMR4
TMR2
TMR4
TMR2
TMR4
TMR2
TMR4
Timer1 is used for all Capture
and Compare operations for
all CCP modules. Timer2 is
used for PWM operations for
all CCP modules. Modules
may share either timer
resource as a common time
base.
Timer3 and Timer4 are not
available.
Timer1 and Timer2 are used
for Capture and Compare or
PWM operations for ECCP1
only (depending on selected
mode).
All other modules use either
Timer3 or Timer4. Modules
may share either timer
resource as a common time
base if they are in
Capture/Compare or PWM
modes.
Timer1 and Timer2 are used
for Capture and Compare or
PWM operations for ECCP1
and ECCP2 only (depending
on the mode selected for each
module). Both modules may
use a timer as a common time
base if they are both in
Capture/Compare or PWM
modes.
The other modules use either
Timer3 or Timer4. Modules
may share either timer
resource as a common time
base if they are in
Capture/Compare or PWM
modes.
Timer3 is used for all Capture
and Compare operations for
all CCP modules. Timer4 is
used for PWM operations for
all CCP modules. Modules
may share either timer
resource as a common time
base.
Timer1 and Timer2 are not
available.
DS39778D-page 198
© 2009 Microchip Technology Inc.