PIC18F67J11-IPT Datasheet, PDF (27/448 Pages) Microchip Technology – 64/80-Pin High-Performance, 1-Mbit Flash Microcontrollers with nanoWatt Technology

PIC18F87J11 FAMILY
TABLE 1-4: PIC18F8XJ1X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number _{Pin Buffer}
80-TQFP ^{Type Type}
Description
RE0/AD8/PMRD/P2D
RE0
AD8
PMRD⁽⁶⁾
P2D
PORTE is a bidirectional I/O port.
4
I/O ST
Digital I/O.
I/O TTL
External memory address/data 8.
I/O
—
Parallel Master Port read strobe.
O
—
ECCP2 PWM output D.
RE1/AD9/PMWR/P2C
RE1
AD9
PMWR⁽⁶⁾
P2C
3
I/O ST
Digital I/O.
I/O TTL
External memory address/data 9.
I/O
—
Parallel Master Port write strobe.
O
—
ECCP2 PWM output C.
RE2/AD10/PMBE/P2B
78
RE2
AD10
PMBE⁽⁶⁾
P2B
RE3/AD11/PMA13/P3C/REFO
77
RE3
AD11
PMA13
P3C⁽³⁾
REFO
I/O ST
I/O TTL
O
—
O
—
I/O ST
I/O TTL
O
—
O
—
O
—
Digital I/O.
External memory address/data 10.
Parallel Master Port byte enable.
ECCP2 PWM output B.
Digital I/O.
External memory address/data 11.
Parallel Master Port address.
ECCP3 PWM output C.
Reference clock out.
RE4/AD12/PMA12/P3B
RE4
AD12
PMA12
P3B⁽³⁾
76
I/O ST
Digital I/O.
I/O TTL
External memory address/data 12.
O
—
Parallel Master Port address.
O
—
ECCP3 PWM output B.
RE5/AD13/PMA11/P1C
RE5
AD13
PMA11
P1C⁽³⁾
RE6/AD14/PMA10/P1B
RE6
AD14
PMA10
P1B⁽³⁾
75
I/O ST
Digital I/O.
I/O TTL
External memory address/data 13.
O
—
Parallel Master Port address.
O
—
ECCP1 PWM output C.
74
I/O ST
Digital I/O.
I/O TTL
External memory address/data 14.
O
—
Parallel Master Port address.
O
—
ECCP1 PWM output B.
RE7/AD15/PMA9/ECCP2/P2A
73
RE7
AD15
PMA9
ECCP2⁽⁴⁾
P2A⁽⁴⁾
I/O ST
I/O TTL
O
—
I/O ST
O
—
Digital I/O.
External memory address/data 15.
Parallel Master Port address.
Capture 2 input/Compare 2 output/PWM2 output.
ECCP2 PWM output A.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I = Input
O
= Output
P = Power
OD = Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared (Extended Microcontroller mode).
2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set).
3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode).
5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).
6: Default assignment for PMP data and control pins when PMPMX Configuration bit is set.
7: Alternate assignment for PMP data and control pins when PMPMX Configuration bit is cleared (programmed).
© 2009 Microchip Technology Inc.
DS39778D-page 27