PIC18F67J11-IPT Datasheet, PDF (346/448 Pages) Microchip Technology – 64/80-Pin High-Performance, 1-Mbit Flash Microcontrollers with nanoWatt Technology

PIC18F87J11 FAMILY
BZ
Branch if Zero
Syntax:
Operands:
Operation:
Status Affected:
BZ n
-128 ≤ n ≤ 127
if Zero bit is ‘1’,
(PC) + 2 + 2n → PC
None
Encoding:
Description:
1110 0000 nnnn nnnn
If the Zero bit is ‘1’, then the program
will branch.
Words:
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
1
Cycles:
Q Cycle Activity:
If Jump:
Q1
Decode
No
operation
If No Jump:
Q1
Decode
1(2)
Q2
Read literal
‘n’
No
operation
Q2
Read literal
‘n’
Q3
Process
Data
No
operation
Q3
Process
Data
Q4
Write to
PC
No
operation
Q4
No
operation
Example:
HERE
Before Instruction
PC
=
After Instruction
If Zero
=
PC
=
If Zero
=
PC
=
BZ Jump
address (HERE)
1;
address (Jump)
0;
address (HERE + 2)
CALL
Subroutine Call
Syntax:
CALL k {,s}
Operands:
0 ≤ k ≤ 1048575
s ∈ [0,1]
Operation:
(PC) + 4 → TOS,
k → PC<20:1>;
if s = 1,
(W) → WS,
(STATUS) → STATUSS,
(BSR) → BSRS
Status Affected:
None
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)
Description:
1110 110s k₇kkk kkkk₀
1111 k₁₉kkk kkkk kkkk₈
Subroutine call of entire 2-Mbyte
memory range. First, return address
(PC + 4) is pushed onto the return
stack. If ‘s’ = 1, the W, STATUS and
BSR registers are also pushed into their
respective shadow registers, WS,
STATUSS and BSRS. If ‘s’ = 0, no
update occurs (default). Then, the
20-bit value ‘k’ is loaded into PC<20:1>.
CALL is a two-cycle instruction.
Words:
2
Cycles:
2
Q Cycle Activity:
Q1
Decode
No
operation
Q2
Read literal
‘k’<7:0>,
No
operation
Q3
Push PC to
stack
No
operation
Q4
Read literal
’k’<19:8>,
Write to PC
No
operation
Example:
HERE
CALL THERE,1
Before Instruction
PC
=
After Instruction
PC
=
TOS =
WS
=
BSRS =
STATUSS =
address (HERE)
address (THERE)
address (HERE + 4)
W
BSR
STATUS
DS39778D-page 346
© 2009 Microchip Technology Inc.