PIC18F67J11-IPT Datasheet, PDF (340/448 Pages) Microchip Technology – 64/80-Pin High-Performance, 1-Mbit Flash Microcontrollers with nanoWatt Technology

PIC18F87J11 FAMILY
BCF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
Bit Clear f
BCF f, b {,a}
0 ≤ f ≤ 255
0≤b≤7
a ∈ [0,1]
0 → f<b>
None
1001 bbba ffff ffff
Bit ‘b’ in register ‘f’ is cleared.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1
Q2
Read
register ‘f’
Q3
Process
Data
Q4
Write
register ‘f’
Example:
BCF
Before Instruction
FLAG_REG = C7h
After Instruction
FLAG_REG = 47h
FLAG_REG, 7, 0
BN
Branch if Negative
Syntax:
Operands:
Operation:
Status Affected:
BN n
-128 ≤ n ≤ 127
if Negative bit is ‘1’,
(PC) + 2 + 2n → PC
None
Encoding:
Description:
1110 0110 nnnn nnnn
If the Negative bit is ‘1’, then the
program will branch.
Words:
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
1
Cycles:
Q Cycle Activity:
If Jump:
Q1
Decode
No
operation
If No Jump:
Q1
Decode
1(2)
Q2
Read literal
‘n’
No
operation
Q2
Read literal
‘n’
Q3
Process
Data
No
operation
Q3
Process
Data
Q4
Write to
PC
No
operation
Q4
No
operation
Example:
HERE
Before Instruction
PC
=
After Instruction
If Negative =
PC
=
If Negative =
PC
=
BN Jump
address (HERE)
1;
address (Jump)
0;
address (HERE + 2)
DS39778D-page 340
© 2009 Microchip Technology Inc.