PIC18F67J11-IPT Datasheet, PDF (80/448 Pages) Microchip Technology – 64/80-Pin High-Performance, 1-Mbit Flash Microcontrollers with nanoWatt Technology

PIC18F87J11 FAMILY
TABLE 5-5: REGISTER FILE SUMMARY (PIC18F87J11 FAMILY) (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Details
on
Page:
TRISJ⁽⁷⁾
TRISH⁽⁷⁾
TRISJ7
TRISH7
TRISJ6
TRISH6
TRISJ5
TRISH5
TRISJ4
TRISH4
TRISJ3
TRISH3
TRISJ2
TRISH2
TRISJ1
TRISH1
TRISJ0 1111 1111 60, 152
TRISH0 1111 1111 60, 150
TRISG
—
—
—
TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 ---1 1111 60, 148
TRISF
TRISF7
TRISF6
TRISF5
TRISF4
TRISF3
TRISF2
TRISF1
—
1111 111- 60, 146
TRISE
TRISE7
TRISE6
TRISE5
TRISE4
TRISE3
TRISE2
TRISE1 TRISE0 1111 1111 60, 143
TRISD
TRISD7
TRISD6
TRISD5
TRISD4
TRISD3
TRISD2
TRISD1 TRISD0 1111 1111 60, 140
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1 TRISC0 1111 1111 60, 138
TRISB
TRISA
LATJ⁽⁷⁾
LATH⁽⁷⁾
TRISB7
TRISA7⁽⁸⁾
LATJ7
LATH7
TRISB6
TRISA6⁽⁸⁾
LATJ6
LATH6
TRISB5
TRISA5
LATJ5
LATH5
TRISB4
TRISA4
LATJ4
LATH4
TRISB3
TRISA3
LATJ3
LATH3
TRISB2
TRISA2
LATJ2
LATH2
TRISB1
TRISA1
LATJ1
LATH1
TRISB0
TRISA0
LATJ0
LATH0
1111 1111
1111 1111
xxxx xxxx
xxxx xxxx
60, 136
60, 134
60, 152
60, 150
LATG
—
—
—
LATG4
LATG3
LATG2
LATG1
LATG0 ---x xxxx 60, 148
LATF
LATF7
LATF6
LATF5
LATF4
LATF3
LATF2
LATF1
—
xxxx xxx- 60, 146
LATE
LATE7
LATE6
LATE5
LATE4
LATE3
LATE2
LATE1
LATE0 xxxx xxxx 60, 143
LATD
LATD7
LATD6
LATD5
LATD4
LATD3
LATD2
LATD1
LATD0 xxxx xxxx 60, 140
LATC
LATC7
LATC6
LATC5
LATC4
LATC3
LATC2
LATC1
LATC0 xxxx xxxx 60, 138
LATB
LATA
PORTJ⁽⁷⁾
PORTH⁽⁷⁾
PORTG
LATB7
LATA7⁽⁸⁾
RJ7
RH7
RDPU
LATB6
LATA6⁽⁸⁾
RJ6
RH6
REPU
LATB5
LATA5
RJ5
RH5
RJPU⁽⁷⁾
LATB4
LATA4
RJ4
RH4
RG4
LATB3
LATA3
RJ3
RH3
RG3
LATB2
LATA2
RJ2
RH2
RG2
LATB1
LATA1
RJ1
RH1
RG1
LATB0
LATA0
RJ0
RH0
RG0
xxxx xxxx
xxxx xxxx
xxxx xxxx
0000 xxxx
000x xxxx
60, 136
60, 134
61, 152
61, 150
61, 148
PORTF
RF7
RF6
RF5
RF4
RF3
RF2
RF1
—
x000 000- 61, 146
PORTE
RE7
RE6
RE5
RE4
RE3
RE2
RE1
RE0 xxxx xxxx 61, 143
PORTD
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0 xxxx xxxx 61, 140
PORTC
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0 xxxx xxxx 61, 138
PORTB
PORTA
RB7
RA7⁽⁸⁾
RB6
RA6⁽⁸⁾
RB5
RA5
RB4
RA4
RB3
RA3
RB2
RA2
RB1
RB0 xxxx xxxx 61, 136
RA1
RA0 000x 0000 61, 134
SPBRGH1 EUSART1 Baud Rate Generator Register High Byte
0000 0000 61, 275
BAUDCON1 ABDOVF
RCIDL
RXDTP
TXCKP
BRG16
—
WUE
ABDEN 0100 0-00 61, 275
SPBRGH2 EUSART2 Baud Rate Generator Register High Byte
0000 0000 61, 275
BAUDCON2 ABDOVF
RCIDL
RXDTP
TXCKP
BRG16
—
WUE
ABDEN 0100 0-00 61, 275
TMR3H
Timer3 Register High Byte
xxxx xxxx 61, 196
TMR3L
Timer3 Register Low Byte
xxxx xxxx 61, 196
T3CON
RD16
T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 61, 196
TMR4
PR4⁽²⁾/
CVRCON⁽³⁾
Timer4 Register
Timer4 Period Register
CVREN
CVROE
CVRR
CVRSS
CVR3
CVR2
CVR1
CVR0
0000 0000
1111 1111
0000 0000
61, 195
61, 196
61, 312
T4CON
—
T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 -000 0000 61, 195
Legend:
Note 1:
2:
3:
4:
5:
6:
7:
8:
9:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Bold indicates shared access SFRs.
Bit 21 of the PC is only available in Serial Programming modes.
Default (legacy) SFR at this address, available when WDTCON<4> = 0.
Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> = 1.
Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
The SSPxMSK registers are only accessible when SSPxCON2<3:0> = 1001.
Alternate names and definitions for these bits when the MSSP modules are operating in I²C™ Slave mode. See Section 19.4.3.2
“Address Masking Modes” for details
These bits and/or registers are only available in 80-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are
shown for 80-pin devices.
These bits are only available in select oscillator modes (FOSC2 Configuration bit = 0); otherwise, they are unimplemented.
The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the physical registers and addresses, but have different
functions determined by the module’s operating mode. See Section 11.1.2 “Data Registers” for more information.
DS39778D-page 80
© 2009 Microchip Technology Inc.