PIC18F67J11-IPT Datasheet, PDF (142/448 Pages) Microchip Technology – 64/80-Pin High-Performance, 1-Mbit Flash Microcontrollers with nanoWatt Technology

PIC18F87J11 FAMILY
TABLE 10-12: PORTE FUNCTIONS
Pin Name
Function
TRIS
Setting
I/O
I/O
Type
Description
RE0/AD8/
RE0
0
PMRD/P2D
1
AD8⁽³⁾
x
x
PMRD⁽⁵⁾
x
x
P2D
0
O
DIG LATE<0> data output.
I
ST PORTE<0> data input.
O
DIG External memory interface, address/data bit 8 output.⁽²⁾
I
TTL External memory interface, data bit 8 input.⁽²⁾
O
DIG Parallel Master Port read strobe pin.
I
TTL Parallel Master Port read pin.
O
DIG ECCP2 Enhanced PWM output, channel D; takes priority over port
and PMP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RE1/AD9/
RE1
0
PMWR/P2C
1
AD9⁽³⁾
x
x
PMWR⁽⁵⁾
x
x
P2C
0
O
DIG LATE<1> data output.
I
ST PORTE<1> data input.
O
DIG External memory interface, address/data bit 9 output.⁽²⁾
I
TTL External memory interface, data bit 9 input.⁽²⁾
O
DIG Parallel Master Port write strobe pin.
I
TTL Parallel Master Port write pin.
O
DIG ECCP2 Enhanced PWM output, channel C; takes priority over port
and PMP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RE2/AD10/
RE2
0
PMBE/P2B
1
AD10⁽³⁾
x
x
PMBE⁽⁵⁾
x
P2B
0
O
DIG LATE<2> data output.
I
ST PORTE<2> data input.
O
DIG External memory interface, address/data bit 10 output.⁽²⁾
I
TTL External memory interface, data bit 10 input.⁽²⁾
O
DIG Parallel Master Port byte enable.
O
DIG ECCP2 Enhanced PWM output, channel B; takes priority over port and
PMP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RE3/AD11/
RE3
0
PMA13/P3C/
1
REFO
AD11⁽³⁾
x
x
PMA13
x
P3C⁽¹⁾
0
O
DIG LATE<3> data output.
I
ST PORTE<3> data input.
O
DIG External memory interface, address/data bit 11 output.⁽²⁾
I
TTL External memory interface, data bit 11 input.⁽²⁾
O
DIG Parallel Master Port address.
O
DIG ECCP3 Enhanced PWM output, channel C; takes priority over port
and PMP data. May be configured for tri-state during Enhanced PWM
shutdown events.
REFO
x
RE4/AD12/
RE4
0
PMA12/P3B
1
AD12⁽³⁾
x
x
PMA12
x
P3B⁽¹⁾
0
O
DIG Reference output clock.
O
DIG LATE<4> data output.
I
ST PORTE<4> data input.
O
DIG External memory interface, address/data bit 12 output.⁽²⁾
I
TTL External memory interface, data bit 12 input.⁽²⁾
O
DIG Parallel Master Port address.
O
DIG ECCP3 Enhanced PWM output, channel B; takes priority over port and
PMP data. May be configured for tri-state during Enhanced PWM
shutdown events.
Legend:
Note 1:
2:
3:
4:
5:
O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Default assignments for P1B/P1C and P3B/P3C when ECCPMX Configuration bit is set (80-pin devices only).
External memory interface I/O takes priority over all other digital and PMP I/O.
Available on 80-pin devices only.
Alternate assignment for ECCP2/P2A when ECCP2MX Configuration bit is cleared (all devices in Microcontroller mode).
Default configuration for PMP (PMPMX Configuration bit = 1).
DS39778D-page 142
© 2009 Microchip Technology Inc.