PIC18F67J11-IPT Datasheet, PDF (342/448 Pages) Microchip Technology – 64/80-Pin High-Performance, 1-Mbit Flash Microcontrollers with nanoWatt Technology

PIC18F87J11 FAMILY
BNOV
Branch if Not Overflow
Syntax:
Operands:
Operation:
Status Affected:
BNOV n
-128 ≤ n ≤ 127
if Overflow bit is ‘0’,
(PC) + 2 + 2n → PC
None
Encoding:
Description:
1110 0101 nnnn nnnn
If the Overflow bit is ‘0’, then the
program will branch.
Words:
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
1
Cycles:
Q Cycle Activity:
If Jump:
Q1
Decode
No
operation
If No Jump:
Q1
Decode
1(2)
Q2
Read literal
‘n’
No
operation
Q2
Read literal
‘n’
Q3
Process
Data
No
operation
Q3
Process
Data
Q4
Write to
PC
No
operation
Q4
No
operation
Example:
HERE
Before Instruction
PC
=
After Instruction
If Overflow =
PC
=
If Overflow =
PC
=
BNOV Jump
address (HERE)
0;
address (Jump)
1;
address (HERE + 2)
BNZ
Branch if Not Zero
Syntax:
Operands:
Operation:
Status Affected:
BNZ n
-128 ≤ n ≤ 127
if Zero bit is ‘0’,
(PC) + 2 + 2n → PC
None
Encoding:
Description:
1110 0001 nnnn nnnn
If the Zero bit is ‘0’, then the program
will branch.
Words:
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
1
Cycles:
Q Cycle Activity:
If Jump:
Q1
Decode
No
operation
If No Jump:
Q1
Decode
1(2)
Q2
Read literal
‘n’
No
operation
Q2
Read literal
‘n’
Q3
Process
Data
No
operation
Q3
Process
Data
Q4
Write to
PC
No
operation
Q4
No
operation
Example:
HERE
Before Instruction
PC
=
After Instruction
If Zero
=
PC
=
If Zero
=
PC
=
BNZ Jump
address (HERE)
0;
address (Jump)
1;
address (HERE + 2)
DS39778D-page 342
© 2009 Microchip Technology Inc.