PIC18F67J11-IPT Datasheet, PDF (134/448 Pages) Microchip Technology – 64/80-Pin High-Performance, 1-Mbit Flash Microcontrollers with nanoWatt Technology

PIC18F87J11 FAMILY
TABLE 10-5: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page:
PORTA
RA7⁽¹⁾
RA6⁽¹⁾
RA5
RA4
RA3
RA2
RA1
RA0
61
LATA
LATA7⁽¹⁾ LATA6⁽¹⁾ LATA5 LATA4 LATA3 LATA2 LATA1 LATA0
60
TRISA
TRISA7⁽¹⁾ TRISA6⁽¹⁾ TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0
60
ANCON0⁽²⁾ PCFG7 PCFG6
—
PCFG4 PCFG3 PCFG2 PCFG1 PCFG0
59
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA.
Note 1: Implemented only in specific oscillator modes (FOSC2 Configuration bit = 0); otherwise read as ‘0’.
2: Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> = 1.
10.3 PORTB, TRISB and
LATB Registers
PORTB is an 8-bit wide, bidirectional port. The corre-
sponding Data Direction register is TRISB. All pins on
PORTB are digital only and tolerate voltages up to
5.5V.
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is
performed by clearing bit, RBPU (INTCON2<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on a Power-on Reset.
Four of the PORTB pins (RB7:RB4) have an
interrupt-on-change feature. Only pins configured as
inputs can cause this interrupt to occur (i.e., any
RB7:RB4 pin configured as an output is excluded from
the interrupt-on-change comparison). The input pins (of
RB7:RB4) are compared with the old value latched on
the last read of PORTB. The “mismatch” outputs of
RB7:RB4 are ORed together to generate the RB Port
Change Interrupt with Flag bit, RBIF (INTCON<0>).
This interrupt can wake the device from
power-managed modes. The user, in the Interrupt
Service Routine, can clear the interrupt in the following
manner:
a) Any read or write of PORTB (except with the
MOVFF (ANY), PORTB instruction). This will
end the mismatch condition.
b) Clear flag bit, RBIF.
A mismatch condition will continue to set flag bit, RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit, RBIF, to be cleared.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
For 80-pin devices, RB3 can be configured as the
alternate peripheral pin for the ECCP2 module and
Enhanced PWM output 2A by clearing the CCP2MX
Configuration bit. This applies only to 80-pin devices
operating in Extended Microcontroller mode. If the
device is in Microcontroller mode, the alternate
assignment for ECCP2 is RE7. As with other ECCP2
configurations, the user must ensure that the TRISB<3>
bit is set appropriately for the intended operation. Ports,
RB1, RB2, RB3, RB4 and RB5, are multiplexed with
the Parallel Master Port address.
EXAMPLE 10-2: INITIALIZING PORTB
CLRF
CLRF
MOVLW
MOVWF
PORTB
LATB
0CFh
TRISB
; Initialize PORTB by
; clearing output
; data latches
; Alternate method to clear
; output data latches
; Value used to initialize
; data direction
; Set RB<3:0> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs
DS39778D-page 134
© 2009 Microchip Technology Inc.