PIC18F67J11-IPT Datasheet, PDF (436/448 Pages) Microchip Technology – 64/80-Pin High-Performance, 1-Mbit Flash Microcontrollers with nanoWatt Technology

PIC18F87J11 FAMILY
BTFSC ............................................................................. 344
BTFSS .............................................................................. 344
BTG .................................................................................. 345
BZ ..................................................................................... 346
C
C Compilers
MPLAB C18 ............................................................. 382
MPLAB C30 ............................................................. 382
Calibration (A/D Converter) .............................................. 301
CALL ................................................................................ 346
CALLW ............................................................................. 375
Capture (CCP Module) ..................................................... 199
Associated Registers ............................................... 201
CCP Pin Configuration ............................................. 199
CCPRxH:CCPRxL Registers ................................... 199
Prescaler .................................................................. 199
Software Interrupt .................................................... 199
Timer1/Timer3 Mode Selection ................................ 199
Capture (ECCP Module) .................................................. 209
Capture/Compare/PWM (CCP) ........................................ 197
Capture Mode. See Capture.
CCP Mode and Timer Resources ............................ 198
CCPRxH Register .................................................... 198
CCPRxL Register ..................................................... 198
Compare Mode. See Compare.
Module Configuration ............................................... 198
Timer Interconnect Configurations ........................... 198
Clock Sources .................................................................... 35
Default System Clock on Reset ................................. 36
Selection Using OSCCON Register ........................... 36
CLRF ................................................................................ 347
CLRWDT .......................................................................... 347
Code Examples
16 x 16 Signed Multiply Routine .............................. 112
16 x 16 Unsigned Multiply Routine .......................... 112
8 x 8 Signed Multiply Routine .................................. 111
8 x 8 Unsigned Multiply Routine .............................. 111
A/D Calibration Routine ........................................... 301
Changing Between Capture Prescalers ................... 199
Computed GOTO Using an Offset Value ................... 69
Erasing a Flash Program Memory Row ..................... 94
Fast Register Stack .................................................... 69
How to Clear RAM (Bank 1) Using Indirect Addressing .
83
Implementing a Real-Time Clock Using a Timer1 Inter-
rupt Service ...................................................... 187
Initializing PORTA .................................................... 132
Initializing PORTB .................................................... 134
Initializing PORTC .................................................... 136
Initializing PORTD .................................................... 138
Initializing PORTE .................................................... 141
Initializing PORTF .................................................... 144
Initializing PORTG ................................................... 146
Initializing PORTH .................................................... 148
Initializing PORTJ .................................................... 151
Loading the SSP1BUF (SSP1SR) Register ............. 226
Reading a Flash Program Memory Word .................. 93
Saving STATUS, WREG and BSR Registers in RAM ...
128
Single-Word Write to Flash Program Memory ........... 97
Writing to Flash Program Memory ............................. 96
Code Protection ............................................................... 315
COMF ............................................................................... 348
Comparator ...................................................................... 303
Analog Input Connection Considerations ................. 306
DS39778D-page 436
Associated Registers ............................................... 310
Configuration ........................................................... 307
Control ..................................................................... 307
Effects of a Reset .................................................... 310
Enable, Input Selection ............................................ 307
Enable, Output Selection ......................................... 307
Interrupts ................................................................. 309
Operation ................................................................. 306
Operation During Sleep ........................................... 310
Reference
Response Time ............................................... 306
Single Comparator ................................................... 306
Comparator Specifications ............................................... 399
Comparator Voltage Reference ....................................... 311
Accuracy and Error .................................................. 313
Associated Registers ............................................... 313
Configuring .............................................................. 312
Connection Considerations ...................................... 313
Effects of a Reset .................................................... 313
Operation During Sleep ........................................... 313
Compare (CCP Module) .................................................. 200
Associated Registers ............................................... 201
CCPRx Register ...................................................... 200
Pin Configuration ..................................................... 200
Software Interrupt .................................................... 200
Timer1/Timer3 Mode Selection ................................ 200
Compare (ECCP Module) ................................................ 209
Special Event Trigger ...................................... 209, 300
Compare (ECCPx Modules)
Special Event Trigger .............................................. 193
Computed GOTO ............................................................... 69
Configuration Bits ............................................................ 315
Configuration Mismatch Reset (CM) .................................. 53
Configuration Register Protection .................................... 329
Core Features
Easy Migration ........................................................... 10
Expanded Memory ....................................................... 9
Extended Instruction Set ............................................. 9
External Memory Bus .................................................. 9
nanoWatt Technology .................................................. 9
Oscillator Options and Features .................................. 9
CPFSEQ .......................................................................... 348
CPFSGT .......................................................................... 349
CPFSLT ........................................................................... 349
Crystal Oscillator/Ceramic Resonator ................................ 37
Customer Change Notification Service ............................ 433
Customer Notification Service ......................................... 433
Customer Support ............................................................ 433
D
Data Addressing Modes .................................................... 83
Comparing Addressing Modes with the Extended In-
struction Set Enabled ........................................ 87
Direct ......................................................................... 83
Indexed Literal Offset ................................................ 86
BSR ................................................................... 88
Instructions Affected .......................................... 86
Mapping Access Bank ....................................... 88
Indirect ....................................................................... 83
Inherent and Literal .................................................... 83
Data Memory ..................................................................... 72
Access Bank .............................................................. 74
Bank Select Register (BSR) ...................................... 72
Extended Instruction Set ........................................... 86
General Purpose Registers ....................................... 74
Memory Map .............................................................. 73
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