PIC18F67J11-IPT Datasheet, PDF (45/448 Pages) Microchip Technology – 64/80-Pin High-Performance, 1-Mbit Flash Microcontrollers with nanoWatt Technology

PIC18F87J11 FAMILY
Note:
The Timer1 oscillator should already be
running prior to entering SEC_RUN mode.
If the T1OSCEN bit is not set when the
SCS1:SCS0 bits are set to ‘01’, entry to
SEC_RUN mode will not occur. If the
Timer1 oscillator is enabled, but not yet
running, device clocks will be delayed until
the oscillator has started. In such situa-
tions, initial oscillator operation is far from
stable and unpredictable operation may
result.
On transitions from SEC_RUN mode to PRI_RUN
mode, the peripherals and CPU continue to be clocked
from the Timer1 oscillator while the primary clock is
started. When the primary clock becomes ready, a
clock switch back to the primary clock occurs (see
Figure 3-2). When the clock switch is complete, the
T1RUN bit is cleared, the OSTS bit is set and the
primary clock is providing the clock. The IDLEN and
SCS bits are not affected by the wake-up; the Timer1
oscillator continues to run.
FIGURE 3-1:
TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE
Q1 Q2 Q3 Q4 Q1
T1OSI
1
OSC1
CPU
Clock
Peripheral
Clock
Program
Counter
PC
2
3
n-1 n
Clock Transition
PC + 2
Q2 Q3 Q4 Q1 Q2 Q3
PC + 4
FIGURE 3-2:
TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL)
Q1
Q2
Q3
Q4 Q1
Q2 Q3 Q4 Q1 Q2 Q3
T1OSI
OSC1
PLL Clock
Output
TOST⁽¹⁾
CPU Clock
Peripheral
Clock
Program
Counter
PC
SCS1:SCS0 Bits Changed
TPLL⁽¹⁾
1 2 n-1 n
Clock
Transition
OSTS Bit Set
PC + 2
PC + 4
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
© 2009 Microchip Technology Inc.
DS39778D-page 45